EPM7128AELC84-7
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 84-LCC (J-Lead) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Series | MAX® 7000A |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 84 |
| ECCN Code | 3A991 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1.27mm |
| Reach Compliance Code | compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | EPM7128 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 2.5/3.33.3V |
| Supply Voltage-Min (Vsup) | 3V |
| Programmable Type | In System Programmable |
| Number of I/O | 68 |
| Clock Frequency | 129.9MHz |
| Propagation Delay | 7.5 ns |
| Number of Gates | 2500 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| Voltage Supply - Internal | 3V~3.6V |
| Delay Time tpd(1) Max | 7.5ns |
| Number of Logic Elements/Blocks | 8 |
| Length | 29.3116mm |
| Width | 29.3116mm |
| RoHS Status | Non-RoHS Compliant |
EPM7128AELC84-7 Overview
Currently, there are 128 macro cells, which are low-power cell sites (towers, antennas, masts) that serve as radio coverage.84-LCC (J-Lead)is the package in which it resides.The device has 68inputs and outputs.The termination of a device is set to [0].There is a QUADterminal position on the electrical part in question.The power source is powered by 3.3Vvolts.There is a part in the family [0].Trayshould be used to package the chip.To ensure its reliability, the operating temperature is set to [0].Ensure that the chip is mounted by Surface Mount.In FPGA terms, it is a type of MAX? 7000Aseries FPGA.This device can also display [0].EPM7128contains its related parts.A digital circuit can be constructed using 2500gates.There are 8 logic elements/blocks, which are fundamental building blocks of field-programmable gate array (FPGA) technology.It operates from 2.5/3.33.3V power supplies.Initially, the maximum supply voltage (Vsup) is 3.6V.It should be possible for Vsup to exceed 3Vat the supply voltage.It is recommended that the clock frequency not exceed 129.9MHz.
EPM7128AELC84-7 Features
84-LCC (J-Lead) package
68 I/Os
The operating temperature of 0°C~70°C TA
2.5/3.33.3V power supplies
EPM7128AELC84-7 Applications
There are a lot of Intel EPM7128AELC84-7 CPLDs applications.
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- D/T registers and latches
- Complex programmable logic devices
- Portable digital devices
- Address decoders
- Network Interface Card (NIC) and Host Bus Adapter (HBA)
- Power Meter SMPS
- Custom state machines
- Code converters
- Handheld digital devices
