EPM7128BFC256-4
| Parameters | |
|---|---|
| In-System Programmable | YES |
| Height Seated (Max) | 3.5mm |
| Length | 17mm |
| Width | 17mm |
| RoHS Status | RoHS Compliant |
| Mount | Surface Mount |
| Package / Case | FBGA |
| Number of Pins | 256 |
| Published | 2008 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Discontinued |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 256 |
| ECCN Code | 3A991 |
| Terminal Finish | Tin/Lead (Sn63Pb37) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 2.5V |
| Terminal Pitch | 1mm |
| Frequency | 333.33MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 256 |
| Qualification Status | Not Qualified |
| Temperature Grade | COMMERCIAL |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Number of I/O | 100 |
| Memory Type | EEPROM |
| Propagation Delay | 4 ns |
| Turn On Delay Time | 4 ns |
| Frequency (Max) | 243.9MHz |
| Programmable Logic Type | EE PLD |
| Number of Gates | 2500 |
| Number of Programmable I/O | 100 |
| Number of Logic Blocks (LABs) | 8 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
EPM7128BFC256-4 Overview
128 macrocells are present in the mobile phone network, which offer radio coverage from a high-power cell tower, antenna, or mast.It is embedded in the FBGA package.The device is programmed with 100 I/Os.There are 256 terminations programmed into the device.As the terminal position of this electrical part is [0], it serves as an important access point for passengers or freight.The power supply voltage is 2.5V.This part is included in Programmable Logic Devices.256pins are programmed on the chip.This device can also display [0].A digital circuit is built using 2500gates.It is recommended that data be stored in [0].A Surface Mountis mounted on this electronic component.A total of 256pins are provided on this board.A maximum voltage of 3.6Vis required for operation.It operates with the minimal supply voltage of 3V.There are 100 Programmable I/Os.This frequency is 333.33MHz.It is recommended that the operating temperature exceed 0°C.It is recommended that the operating temperature be lower than 70°C.8logic blocks (LABs) make up this circuit.The maximum frequency should not exceed 243.9MHz.There are several types of programmable logic that can be categorized as EE PLD.
EPM7128BFC256-4 Features
FBGA package
100 I/Os
256 pin count
256 pins
8 logic blocks (LABs)
EPM7128BFC256-4 Applications
There are a lot of Altera EPM7128BFC256-4 CPLDs applications.
- Configurable Addressing of I/O Boards
- PULSE WIDTH MODULATION (PWM)
- Bootloaders for FPGAs
- Boolean function generators
- Power up sequencing
- SUPERVISORY FUNCTION (LVD AND WATCHDOG)
- Synchronous or asynchronous mode
- Address decoders
- TIMERS/COUNTERS
- Preset swapping
