Parameters |
Mount |
Surface Mount |
Package / Case |
PLCC |
Number of Pins |
84 |
Published |
1998 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
2 |
Number of Terminations |
84 |
ECCN Code |
EAR99 |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Max Operating Temperature |
70°C |
Min Operating Temperature |
0°C |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Peak Reflow Temperature (Cel) |
220 |
Supply Voltage |
5V |
Terminal Pitch |
1.27mm |
Frequency |
100MHz |
Time@Peak Reflow Temperature-Max (s) |
30 |
Pin Count |
84 |
Operating Supply Voltage |
5V |
Temperature Grade |
COMMERCIAL |
Max Supply Voltage |
5.25V |
Min Supply Voltage |
4.75V |
Number of I/O |
68 |
Memory Type |
EEPROM |
Propagation Delay |
15 ns |
Turn On Delay Time |
15 ns |
Frequency (Max) |
125MHz |
Programmable Logic Type |
EE PLD |
Number of Gates |
2500 |
Number of Programmable I/O |
68 |
Number of Logic Blocks (LABs) |
8 |
Speed Grade |
15 |
Output Function |
MACROCELL |
Number of Macro Cells |
128 |
JTAG BST |
NO |
In-System Programmable |
NO |
Length |
29.3116mm |
Width |
29.3116mm |
Radiation Hardening |
No |
RoHS Status |
RoHS Compliant |
Lead Free |
Contains Lead |
EPM7128ELC84-15 Overview
There are 128 macro cells in the network, which are high-power cell sites that provide radio coverage (tower, antenna, or mast) for a mobile phone network.The item is enclosed in a PLCC package.The device has 68inputs and outputs.Devices are programmed with terminations of [0].The terminal position of this electrical component is QUAD.It is powered from a supply voltage of 5V.The part is included in Programmable Logic Devices.Chips are programmed with 84 pins.2500gates are devices that serve as building blocks for digital circuits.If high efficiency is to be achieved, the supply voltage should be maintained at [0].In this case, EEPROMwill be used to store the data.It is mounted by Surface Mount.There are 84 pins embedded in the device.It operates at a maximum supply voltage of 5.25V volts.In order for it to operate, a supply voltage of 4.75Vis required.A total of 68programmable I/Os are available.A frequency of 100MHzcan be achieved.It is recommended that the operating temperature be higher than 0°C.The operating temperature should be lower than 70°C.The system consists of 8 logic blocks (LABs).Maximum frequency should be less than 125MHz.This kind of FPGA is composed of EE PLD.
EPM7128ELC84-15 Features
PLCC package
68 I/Os
84 pin count
84 pins
8 logic blocks (LABs)
EPM7128ELC84-15 Applications
There are a lot of Altera EPM7128ELC84-15 CPLDs applications.
- DMA control
- Digital designs
- Cross-Matrix Switch
- Multiple DIP Switch Replacement
- Timing control
- Field programmable gate
- Auxiliary Power Supply Isolated and Non-isolated
- Random logic replacement
- Storage Cards and Storage Racks
- State machine design