EPM7128SLC84-6N
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Package / Case | PLCC |
| Number of Pins | 84 |
| Published | 1998 |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 84 |
| Termination | SMD/SMT |
| ECCN Code | EAR99 |
| Terminal Finish | MATTE TIN (472) OVER COPPER |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
| Frequency | 147.1MHz |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Pin Count | 84 |
| Operating Supply Voltage | 5V |
| Temperature Grade | COMMERCIAL |
| Max Supply Voltage | 5.25V |
| Min Supply Voltage | 4.75V |
| Number of I/O | 68 |
| Memory Type | EEPROM |
| Propagation Delay | 6 ns |
| Turn On Delay Time | 6 ns |
| Frequency (Max) | 147.1MHz |
| Programmable Logic Type | EE PLD |
| Number of Gates | 2500 |
| Number of Programmable I/O | 68 |
| Number of Logic Blocks (LABs) | 8 |
| Speed Grade | 6 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
EPM7128SLC84-6N Overview
In the mobile phone network, there are 128macro cells, which are cells with high-power antennas and towers.The item is packaged with PLCC.It is equipped with 68I/O ports.Devices are programmed with terminations of [0].The terminal position of this electrical component is QUAD.The power supply voltage is 5V.It is a part of the family [0].Chips are programmed with 84 pins.The device can also be used to find [0].A digital circuit is built using 2500gates.High efficiency requires a voltage supply of [0].EEPROM is adopted for storing data.In this case, it is mounted by Surface Mount.The device is designed with pins [0].A voltage of 5.25V is the maximum supply voltage for this device.A minimum supply voltage of 4.75V is required for it to operate.There are 68 programmable I/Os, which are method of data transmissions, via input/output (I/O), between a central processing unit (CPU) and a peripheral device, such as a network adapter or a Parallel ATA storage device. It is possible to achieve a frequency of 147.1MHz.It is recommended that the operating temperature exceed 0°C.The operating temperature should be lower than 70°C.The system consists of 8 logic blocks (LABs).It is recommended that the maximal frequency be less than 0.A programmable logic type is classified as EE PLD.
EPM7128SLC84-6N Features
PLCC package
68 I/Os
84 pin count
84 pins
8 logic blocks (LABs)
EPM7128SLC84-6N Applications
There are a lot of Altera EPM7128SLC84-6N CPLDs applications.
- Configurable Addressing of I/O Boards
- Address decoding
- Discrete logic functions
- DMA control
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- Preset swapping
- Software-driven hardware configuration
- Bootloaders for FPGAs
- D/T registers and latches
- Software Configuration of Add-In Boards
