EPM7128SQC160-7F
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Package / Case | PQFP |
| Number of Pins | 160 |
| Packaging | Bulk |
| Published | 1998 |
| JESD-609 Code | e0 |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 160 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Pin Count | 160 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.25V |
| Power Supplies | 3.3/55V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 4.75V |
| Number of I/O | 100 |
| Clock Frequency | 166.7MHz |
| Propagation Delay | 7.5 ns |
| Programmable Logic Type | EE PLD |
| Number of Gates | 2500 |
| Number of Logic Blocks (LABs) | 8 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height Seated (Max) | 4.07mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Contains Lead |
EPM7128SQC160-7F Overview
There are 128 macro cells, which provide radio coverage via high-power cell towers, antennas or masts in a mobile phone network.It is part of the PQFP package.There are 100 I/Os programmed in it.The termination of a device is set to [0].This electrical part has a terminal position of QUADand is connected to the ground.A voltage of 5Vprovides power to the device.This part is part of the family [0].Package the chip by Bulk.It is equipped with 160 pin count.When using this device, YEScan also be found.It is possible to construct digital circuits using 2500gates, which are devices that serve as building blocks.The electronic part is mounted by Surface Mount.There are 160 pins on the device.It runs on a voltage of 3.3/55Vvolts.In order to ensure proper operation, a maximum supply voltage (Vsup) of 5.25V is required.It is recommended that the operating temperature be greater than 0°C.There should be a temperature below 70°Cat the time of operation.The logic block consists of 8 l logic blocks (LABs).If the supply voltage (Vsup) is greater than 4.75V, then the device will work properly.The clock frequency should not exceed 166.7MHz.Programmable logic types can be divided into EE PLD.
EPM7128SQC160-7F Features
PQFP package
100 I/Os
160 pin count
160 pins
3.3/55V power supplies
8 logic blocks (LABs)
EPM7128SQC160-7F Applications
There are a lot of Altera EPM7128SQC160-7F CPLDs applications.
- Wide Vin Industrial low power SMPS
- Address decoders
- ON-CHIP OSCILLATOR CIRCUIT
- I/O expansion
- Handheld digital devices
- Power up sequencing
- Digital designs
- Multiple DIP Switch Replacement
- Cross-Matrix Switch
- Code converters
