EPM7192EQC160-20
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Package / Case | PQFP |
| Number of Pins | 160 |
| Published | 1998 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Discontinued |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 160 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Frequency | 83.33MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 160 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 5V |
| Temperature Grade | COMMERCIAL |
| Max Supply Voltage | 5.25V |
| Min Supply Voltage | 4.75V |
| Number of I/O | 124 |
| Memory Type | EEPROM |
| Propagation Delay | 20 ns |
| Turn On Delay Time | 20 ns |
| Frequency (Max) | 90.9MHz |
| Programmable Logic Type | EE PLD |
| Number of Gates | 3750 |
| Number of Programmable I/O | 124 |
| Number of Logic Blocks (LABs) | 12 |
| Speed Grade | 20 |
| Output Function | MACROCELL |
| Number of Macro Cells | 192 |
| JTAG BST | NO |
| In-System Programmable | NO |
| Height Seated (Max) | 4.07mm |
| Length | 28mm |
| Width | 28mm |
| RoHS Status | RoHS Compliant |
EPM7192EQC160-20 Overview
192macrocells exist, which are cells in a mobile phone network that are primarily composed of high-power towers, antennas, or masts.In the PQFPpackage, you will find it.It is programmed with 124 I/Os.160terminations are programmed into the device.The terminal position of this electrical component is QUAD.A voltage of 5Vprovides power to the device.The part is included in Programmable Logic Devices.There are 160 pins on the chip.It is also characterized by CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V.A digital circuit is built using 3750gates.In order to achieve high efficiency, the supply voltage should be maintained at [0].It is adopted to store data in [0].In this case, Surface Mountis used to mount the electronic component.The device has a pinout of [0].This device operates at a voltage of 5.25V when the maximum supply voltage is applied.The device is designed to operate with a minimal supply voltage of 4.75VV.A total of 124Programmable I/Os are present.There is 83.33MHz frequency that can be achieved.Operating temperatures should be higher than 0°C.It is recommended to keep the operating temperature below 70°C.It is composed of 12 logic blocks (LABs).It is recommended that the maximum frequency is less than 0.In programmable logic, a type of logic can be categorized as EE PLD.
EPM7192EQC160-20 Features
PQFP package
124 I/Os
160 pin count
160 pins
12 logic blocks (LABs)
EPM7192EQC160-20 Applications
There are a lot of Altera EPM7192EQC160-20 CPLDs applications.
- Auxiliary Power Supply Isolated and Non-isolated
- Software Configuration of Add-In Boards
- Interface bridging
- Bootloaders for FPGAs
- I/O expansion
- Dedicated input registers
- Power Meter SMPS
- STANDARD SERIAL INTERFACE UART
- D/T registers and latches
- Network Interface Card (NIC) and Host Bus Adapter (HBA)
