Parameters |
Number of Terminations |
100 |
Terminal Finish |
TIN LEAD |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
220 |
Supply Voltage |
2.5V |
Terminal Pitch |
1mm |
Reach Compliance Code |
compliant |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
JESD-30 Code |
S-PBGA-B100 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
2.625V |
Power Supplies |
1.8/3.32.5V |
Supply Voltage-Min (Vsup) |
2.375V |
Programmable Type |
In System Programmable |
Number of I/O |
84 |
Clock Frequency |
95.2MHz |
Propagation Delay |
10 ns |
Number of Gates |
5000 |
Output Function |
MACROCELL |
Number of Macro Cells |
256 |
JTAG BST |
YES |
Number of Dedicated Inputs |
4 |
Voltage Supply - Internal |
2.375V~2.625V |
Delay Time tpd(1) Max |
10ns |
Number of Logic Elements/Blocks |
16 |
Height Seated (Max) |
1.7mm |
Length |
11mm |
Width |
11mm |
RoHS Status |
Non-RoHS Compliant |
Mounting Type |
Surface Mount |
Package / Case |
100-LBGA |
Surface Mount |
YES |
Operating Temperature |
0°C~70°C TA |
Packaging |
Tray |
Series |
MAX® 7000B |
JESD-609 Code |
e0 |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
EPM7256BFC100-10 Overview
There are 256 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).The item is enclosed in a 100-LBGA package.There are 84 I/Os programmed in it.Devices are programmed with terminations of [0].Its terminal position is BOTTOM.Power is supplied by a voltage of 2.5V volts.The part belongs to Programmable Logic Devices family.Ideally, the chip should be packaged by Tray.Ensure its reliability by operating at [0].It is mounted in the way of Surface Mount.The MAX? 7000Bseries comprises this type of FPGA.If you use this device, you will also find [0].It is possible to construct digital circuits using 5000gates, which are devices that serve as building blocks.This logic block consists of 16logic elements.The system runs on a power supply of 1.8/3.32.5V watts.The maximal supply voltage (Vsup) reaches 2.625V.The status of input signals is determined by 4dedicated inputs.Voltage supply (Vsup) should be higher than 2.375V.The clock frequency should not exceed 95.2MHz.
EPM7256BFC100-10 Features
100-LBGA package
84 I/Os
The operating temperature of 0°C~70°C TA
1.8/3.32.5V power supplies
EPM7256BFC100-10 Applications
There are a lot of Intel EPM7256BFC100-10 CPLDs applications.
- Pattern recognition
- Synchronous or asynchronous mode
- Digital systems
- White goods (Washing, Cold, Aircon ,...)
- Multiple Clock Source Selection
- Preset swapping
- Dedicated input registers
- Boolean function generators
- ROM patching
- Timing control