EPM7256SRI208-10
| Parameters | |
|---|---|
| Power Supplies | 3.3/55V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Programmable Type | In System Programmable |
| Number of I/O | 164 |
| Clock Frequency | 125MHz |
| Propagation Delay | 10 ns |
| Number of Gates | 5000 |
| Output Function | MACROCELL |
| Number of Macro Cells | 256 |
| JTAG BST | YES |
| Voltage Supply - Internal | 4.5V~5.5V |
| Delay Time tpd(1) Max | 10ns |
| Number of Logic Elements/Blocks | 16 |
| Height Seated (Max) | 4.1mm |
| Length | 28mm |
| Width | 28mm |
| RoHS Status | Non-RoHS Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 208-BFQFP Exposed Pad |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tray |
| Series | MAX® 7000S |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 208 |
| Terminal Finish | TIN/LEAD (SN/PB) |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 20 |
| Base Part Number | EPM7256 |
| JESD-30 Code | S-PQFP-G208 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.5V |
EPM7256SRI208-10 Overview
There are 256 macro cells, which are cells in a mobile phone network that provides radio coverage served by a high-power cell site (tower, antenna or mast).The item is packaged with 208-BFQFP Exposed Pad.There are 164 I/Os programmed in it.The device is programmed with 208 terminations.This electrical part has a terminal position of QUADand is connected to the ground.A voltage of 5V is used as the power supply for this device.There is a part in the family [0].It is recommended to package the chip by Tray.To ensure its reliability, the operating temperature is set to [0].It is mounted in the way of Surface Mount.The MAX? 7000Sseries FPGA is one of these types.The EPM7256contains its related parts.A digital circuit can be constructed using 5000gates.There are 16 logic elements/blocks, which are fundamental building blocks of field-programmable gate array (FPGA) technology.The system runs on a power supply of 3.3/55V watts.Initially, the maximum supply voltage (Vsup) is 5.5V.It should be possible for Vsup to exceed 4.5Vat the supply voltage.This device should not have an clock frequency greater than 125MHz.
EPM7256SRI208-10 Features
208-BFQFP Exposed Pad package
164 I/Os
The operating temperature of -40°C~85°C TA
3.3/55V power supplies
EPM7256SRI208-10 Applications
There are a lot of Intel EPM7256SRI208-10 CPLDs applications.
- Parity generators
- USB Bus
- I/O PORTS (MCU MODULE)
- I/O expansion
- Wide Vin Industrial low power SMPS
- Power up sequencing
- Reset swapping
- Handheld digital devices
- High speed graphics processing
- PULSE WIDTH MODULATION (PWM)
