Parameters |
Mount |
Surface Mount |
Package / Case |
PLCC |
Number of Pins |
84 |
JESD-609 Code |
e3 |
Part Status |
Discontinued |
Number of Terminations |
84 |
ECCN Code |
EAR99 |
Terminal Finish |
MATTE TIN |
Max Operating Temperature |
70°C |
Min Operating Temperature |
0°C |
HTS Code |
8542.39.00.01 |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Peak Reflow Temperature (Cel) |
245 |
Supply Voltage |
5V |
Terminal Pitch |
1.27mm |
Time@Peak Reflow Temperature-Max (s) |
40 |
Pin Count |
84 |
Qualification Status |
Not Qualified |
Temperature Grade |
COMMERCIAL |
Max Supply Voltage |
5.25V |
Min Supply Voltage |
4.75V |
Number of I/O |
60 |
Memory Type |
EEPROM |
Clock Frequency |
144.9MHz |
Propagation Delay |
10.8 ns |
Programmable Logic Type |
EE PLD |
Number of Gates |
6000 |
Number of Logic Blocks (LABs) |
20 |
Output Function |
MACROCELL |
Number of Macro Cells |
320 |
Height |
3.81mm |
Length |
29.31mm |
Width |
29.31mm |
RoHS Status |
RoHS Compliant |
EPM9320ALC84-10N Overview
There are 320 macro cells in the network, which are high-power cell sites that provide radio coverage (tower, antenna, or mast) for a mobile phone network.A PLCC package contains the item.There are 60 I/Os programmed in it.Terminations of devices are set to [0].As the terminal position of this electrical part is [0], it serves as an important access point for passengers or freight.The power source is powered by 5Vvolts.Chips are programmed with 84 pins.In digital circuits, there are 6000gates, which act as a basic building block.EEPROM is adopted for storing data.In this case, it is mounted by Surface Mount.The device has a pinout of [0].A voltage of 5.25V is the maximum supply voltage for this device.In order for it to operate, a supply voltage of 4.75Vis required.Operating temperatures should be higher than 0°C.It is recommended that the operating temperature be below 70°C.Its basic building block is composed of 20 logic blocks (LABs).This device should not have an clock frequency greater than 144.9MHz.Programmable logic types can be divided into EE PLD.
EPM9320ALC84-10N Features
PLCC package
60 I/Os
84 pin count
84 pins
20 logic blocks (LABs)
EPM9320ALC84-10N Applications
There are a lot of Altera EPM9320ALC84-10N CPLDs applications.
- Page register
- Complex programmable logic devices
- Pattern recognition
- Bootloaders for FPGAs
- State machine control
- Cross-Matrix Switch
- LED Lighting systems
- Programmable power management
- State machine design
- Power up sequencing