Parameters |
Mount |
Surface Mount |
Published |
1994 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Part Status |
Discontinued |
Number of Terminations |
208 |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Max Operating Temperature |
70°C |
Min Operating Temperature |
0°C |
Additional Feature |
580 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
220 |
Supply Voltage |
5V |
Terminal Pitch |
0.5mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
Pin Count |
208 |
JESD-30 Code |
S-PQFP-G208 |
Qualification Status |
Not Qualified |
Power Supplies |
3.3/55V |
Temperature Grade |
COMMERCIAL |
Supply Voltage-Min (Vsup) |
4.75V |
Number of I/O |
139 |
Clock Frequency |
117.6MHz |
Propagation Delay |
16.2 ns |
Programmable Logic Type |
EE PLD |
Number of Gates |
8000 |
Number of Logic Blocks (LABs) |
25 |
Output Function |
MACROCELL |
Number of Macro Cells |
400 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
4.1mm |
Length |
28mm |
Width |
28mm |
RoHS Status |
RoHS Compliant |
EPM9400RC208-15 Overview
This network has 400macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).As you can see, this device has 139 I/O ports programmed into it.There is a 208terminations set on devices.The terminal position of this electrical part is QUAD, which serves as an important access point for passengers or freight.There is 5V voltage supply for this device.This part is included in Programmable Logic Devices.It is programmed with 208 pins.If this device is used, you will also be able to find [0].In digital circuits, 8000gates serve as building blocks.Surface Mountis the mounting point of this electronic part.A total of 3.3/55V power supplies are needed to run it.It is recommended that the operating temperature exceeds 0°C.The operating temperature should be lower than 70°C.Its basic building block is composed of 25 logic blocks (LABs).Voltage supply (Vsup) should be higher than 4.75V.The clock frequency of this device should not exceed 117.6MHz.A programmable logic type is categorized as EE PLD.
EPM9400RC208-15 Features
139 I/Os
208 pin count
3.3/55V power supplies
25 logic blocks (LABs)
EPM9400RC208-15 Applications
There are a lot of Altera EPM9400RC208-15 CPLDs applications.
- ON-CHIP OSCILLATOR CIRCUIT
- USB Bus
- Portable digital devices
- Programmable power management
- Interface bridging
- Complex programmable logic devices
- Field programmable gate
- Parity generators
- Bootloaders for FPGAs
- I/O PORTS (MCU MODULE)