EPM9400RC208-20
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Published | 1994 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Discontinued |
| Number of Terminations | 208 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | 580 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 208 |
| JESD-30 Code | S-PQFP-G208 |
| Qualification Status | Not Qualified |
| Power Supplies | 3.3/55V |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Min (Vsup) | 4.75V |
| Number of I/O | 139 |
| Clock Frequency | 100MHz |
| Propagation Delay | 23.2 ns |
| Programmable Logic Type | EE PLD |
| Number of Gates | 8000 |
| Number of Logic Blocks (LABs) | 25 |
| Output Function | MACROCELL |
| Number of Macro Cells | 400 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height Seated (Max) | 4.1mm |
| Length | 28mm |
| Width | 28mm |
| RoHS Status | RoHS Compliant |
EPM9400RC208-20 Overview
There are 400 macro cells in the network, which are high-power cell sites that provide radio coverage (tower, antenna, or mast) for a mobile phone network.As a result, it has 139 I/O ports programmed.208terminations have been programmed into the device.As the terminal position of this electrical part is [0], it serves as an important access point for passengers and freight.The power source is powered by 5Vvolts.It belongs to the family [0].There are 208 pins on the chip.The device can also be used to find [0].A digital circuit can be constructed using 8000gates.This device is mounted by Surface Mount.There is 3.3/55V power supply available for it.There should be a temperature above 0°Cat the time of operation.A temperature lower than 70°Cis recommended for operation.In its simplest form, it consists of 25 logic blocks (LABs).It should be possible for Vsup to exceed 4.75Vat the supply voltage.The clock frequency of the device should not exceed 100MHz.It is possible to classify programmable logic as EE PLD.
EPM9400RC208-20 Features
139 I/Os
208 pin count
3.3/55V power supplies
25 logic blocks (LABs)
EPM9400RC208-20 Applications
There are a lot of Altera EPM9400RC208-20 CPLDs applications.
- Pattern recognition
- Field programmable gate
- White goods (Washing, Cold, Aircon ,...)
- Boolean function generators
- Software-Driven Hardware Configuration
- Synchronous or asynchronous mode
- Random logic replacement
- USB Bus
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- I2C BUS INTERFACE
