Parameters |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
28-LCC (J-Lead) |
Number of Pins |
28 |
Operating Temperature |
0°C~75°C TA |
Packaging |
Tube |
Published |
2000 |
Series |
GAL®20V8 |
JESD-609 Code |
e0 |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
28 |
ECCN Code |
EAR99 |
Additional Feature |
REGISTER PRELOAD; POWER-UP RESET |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Supply Voltage |
5V |
Terminal Pitch |
1.27mm |
Reach Compliance Code |
unknown |
Frequency |
41.7MHz |
Base Part Number |
GAL20V8 |
Pin Count |
28 |
Number of Outputs |
8 |
Qualification Status |
Not Qualified |
Power Supplies |
5V |
Programmable Type |
EE PLD |
Max Supply Voltage |
5.25V |
Min Supply Voltage |
4.75V |
Number of I/O |
8 |
Nominal Supply Current |
55mA |
Propagation Delay |
25 ns |
Turn On Delay Time |
25 ns |
Architecture |
PAL-TYPE |
Output Function |
MACROCELL |
Number of Macro Cells |
8 |
Number of Dedicated Inputs |
12 |
Voltage Supply - Internal |
4.75V~5.25V |
Number of Product Terms |
64 |
Height Seated (Max) |
4.572mm |
Length |
11.5062mm |
Width |
11.5062mm |
RoHS Status |
Non-RoHS Compliant |
Lead Free |
Lead Free |
GAL20V8B-25QJ Overview
There are 8 macro cells, which are cells in a mobile phone network that provides radio coverage served by a high-power cell site (tower, antenna or mast).It is contained in package [0].The device has 8inputs and outputs.There are 28 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.This electrical component has a terminal position of 0.Power is provided by a supply voltage of 5V volts.The part belongs to Programmable Logic Devices family.The chip should be packaged by Tube.The operating temperature of the machine is 0°C~75°C TA to ensure its reliability.The chip should be mounted by Surface Mount.In FPGA terms, it is a type of GAL?20V8series FPGA.Chips are programmed with 28 pins.The device can also be used to find [0].Its related parts can be found in the [0].In this case, it is mounted by Surface Mount.It is designed with 28 pins.A maximum voltage of 5.25Vis required for operation.A minimum supply voltage of 4.75V is required for this device to operate.A power supply of 5Vvolts is required to operate this device.This frequency is 41.7MHz.To detect input signals, there are 12 dedicated inputs.It is configured with 8 output.It is associated with 64product terms.
GAL20V8B-25QJ Features
28-LCC (J-Lead) package
8 I/Os
The operating temperature of 0°C~75°C TA
28 pin count
28 pins
5V power supplies
8 outputs
GAL20V8B-25QJ Applications
There are a lot of Lattice Semiconductor Corporation GAL20V8B-25QJ CPLDs applications.
- Network Interface Card (NIC) and Host Bus Adapter (HBA)
- Digital systems
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- ON-CHIP OSCILLATOR CIRCUIT
- STANDARD SERIAL INTERFACE UART
- Custom state machines
- Multiple Clock Source Selection
- Battery operated portable devices
- Programmable power management
- Parity generators