HEF4027BP,652
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2011 |
| Series | 4000B |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | MATTE TIN |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 3V~15V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 4027 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Min (Vsup) | 3V |
| Load Capacitance | 50pF |
| Clock Frequency | 30MHz |
| Current - Quiescent (Iq) | 16μA |
| Current - Output High, Low | 3mA 3mA |
| Output Polarity | COMPLEMENTARY |
| Max I(ol) | 0.00036 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 60ns @ 15V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 7.5pF |
| fmax-Min | 4 MHz |
| Max Frequency@Nom-Sup | 4000000Hz |
| Height Seated (Max) | 4.7mm |
| RoHS Status | ROHS3 Compliant |
HEF4027BP,652 Overview
In the form of 16-DIP (0.300, 7.62mm), it has been packaged. There is an embedded version in the package Tube. Differentialis the output configured for it. The trigger configured with it uses Positive Edge. It is mounted in the way of Through Hole. The JK flip flop operates at a voltage of 3V~15V. It is operating at -40°C~85°C TA. A flip flop of this type is classified as a JK Type. JK flip flop belongs to the 4000Bseries of FPGAs. Its output frequency should not exceed 30MHz Hz. D latch consists of 2 elements. This process consumes 16μA quiescents. A total of 16terminations have been recorded. If you search by 4027, you will find similar parts. Power is provided by a 5V supply. A JK flip flop with a 7.5pFfarad input capacitance is used here. It is included in FF/Latches. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 3V.
HEF4027BP,652 Features
Tube package
4000B series
HEF4027BP,652 Applications
There are a lot of NXP USA Inc. HEF4027BP,652 Flip Flops applications.
- Guaranteed simultaneous switching noise level
- Individual Asynchronous Resets
- Buffered Clock
- ATE
- Patented noise
- ESCC
- Computing
- Computers
- ESD protection
- Counters
