ISPLSI 5128VE-100LT128
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 128-LQFP |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Published | 2000 |
| Series | ispLSI® 5000VE |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 128 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn85Pb15) |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | ISPLSI 5128 |
| Pin Count | 128 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 2.5/3.33.3V |
| Supply Voltage-Min (Vsup) | 3V |
| Programmable Type | In System Programmable |
| Number of I/O | 96 |
| Clock Frequency | 67MHz |
| Propagation Delay | 10 ns |
| Number of Gates | 6000 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| Voltage Supply - Internal | 3V~3.6V |
| Delay Time tpd(1) Max | 10ns |
| Number of Logic Elements/Blocks | 4 |
| Height Seated (Max) | 1.6mm |
| RoHS Status | Non-RoHS Compliant |
ISPLSI 5128VE-100LT128 Overview
This network has 128macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).A 128-LQFP package contains the item.As a result, it has 96 I/O ports programmed.It is programmed that device terminations will be 128 .This electrical part is wired with a terminal position of QUAD.It is powered by a voltage of 3.3V volts.The part belongs to Programmable Logic Devices family.Trayshould be used to package the chip.To ensure reliability, the device operates at a temperature of [0].Mount the chip by Surface Mount.As part of the ispLSI? 5000VEseries, it is a type of FPGA.The chip is programmed with 128 pins.It is also characterized by YES.Its related parts can be found in the [0].A digital circuit can be constructed using 6000gates.4logic blocks/elements are present.Currently, it is powered by 2.5/3.33.3Vsources.The maximal supply voltage (Vsup) reaches 3.6V.In order to operate properly, the supply voltage (Vsup) should be greater than 3V.It is recommended that the clock frequency not exceed 67MHz.
ISPLSI 5128VE-100LT128 Features
128-LQFP package
96 I/Os
The operating temperature of 0°C~70°C TA
128 pin count
2.5/3.33.3V power supplies
ISPLSI 5128VE-100LT128 Applications
There are a lot of Lattice Semiconductor Corporation ISPLSI 5128VE-100LT128 CPLDs applications.
- TIMERS/COUNTERS
- Portable digital devices
- Digital multiplexers
- Random logic replacement
- D/T registers and latches
- White goods (Washing, Cold, Aircon ,...)
- Bootloaders for FPGAs
- Code converters
- Discrete logic functions
- Address decoding
