Parameters |
Mounting Type |
Surface Mount |
Package / Case |
388-BBGA |
Surface Mount |
YES |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tray |
Published |
2002 |
Series |
ispLSI® 5000VE |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
388 |
ECCN Code |
EAR99 |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
225 |
Supply Voltage |
3.3V |
Terminal Pitch |
1.27mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
Base Part Number |
ISPLSI 5512 |
Pin Count |
388 |
JESD-30 Code |
S-PBGA-B388 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
3.6V |
Power Supplies |
2.5/3.33.3V |
Supply Voltage-Min (Vsup) |
3V |
Programmable Type |
In System Programmable |
Number of I/O |
256 |
Clock Frequency |
87MHz |
Propagation Delay |
7.5 ns |
Number of Gates |
24000 |
Output Function |
MACROCELL |
Number of Macro Cells |
512 |
JTAG BST |
YES |
Voltage Supply - Internal |
3V~3.6V |
Delay Time tpd(1) Max |
7.5ns |
Number of Logic Elements/Blocks |
16 |
Height Seated (Max) |
3.25mm |
Length |
35mm |
Width |
35mm |
RoHS Status |
Non-RoHS Compliant |
ISPLSI 5512VE-125LB388I Overview
There are 512 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).It is embedded in the 388-BBGA package.This device has 256 I/O ports programmed into it.It is programmed that device terminations will be 388 .This electrical part is wired with a terminal position of BOTTOM.There is 3.3V voltage supply for this device.It is included in Programmable Logic Devices.Trayis the packaging method.A reliable operation is ensured by the operating temperature of [0].It is recommended that Surface Mountholds the chip in place.The FPGA belongs to the ispLSI? 5000VE series.With 388pins programmed, the chip is ready to use.This device is also capable of displaying [0].The ISPLSI 5512shows its related parts.It is possible to construct digital circuits using 24000gates, which are devices that serve as building blocks.There are 16 logic elements/blocks, which are fundamental building blocks of field-programmable gate array (FPGA) technology.It runs on 2.5/3.33.3Vvolts of power.3.6Vis the maximum supply voltage (Vsup).Voltage supply (Vsup) should be higher than 3V.It is recommended that the clock frequency not exceed 87MHz.
ISPLSI 5512VE-125LB388I Features
388-BBGA package
256 I/Os
The operating temperature of -40°C~85°C TA
388 pin count
2.5/3.33.3V power supplies
ISPLSI 5512VE-125LB388I Applications
There are a lot of Lattice Semiconductor Corporation ISPLSI 5512VE-125LB388I CPLDs applications.
- PULSE WIDTH MODULATION (PWM)
- Handheld digital devices
- Complex programmable logic devices
- Wide Vin Industrial low power SMPS
- INTERRUPT SYSTEM
- Portable digital devices
- Digital multiplexers
- Custom shift registers
- Programmable power management
- High speed graphics processing