LA4064V-75TN48E
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 48-TQFP |
| Number of Pins | 48 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tray |
| Published | 2000 |
| Series | LA-ispMACH |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 48 |
| ECCN Code | EAR99 |
| Terminal Finish | Matte Tin (Sn) |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Frequency | 168MHz |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | LA4064 |
| Pin Count | 48 |
| Qualification Status | Not Qualified |
| Programmable Type | In System Programmable |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Operating Supply Current | 12mA |
| Number of I/O | 32 |
| Nominal Supply Current | 12mA |
| Memory Type | EEPROM |
| Propagation Delay | 7.5 ns |
| Turn On Delay Time | 7.5 ns |
| Screening Level | AEC-Q100 |
| Number of Logic Blocks (LABs) | 4 |
| Output Function | MACROCELL |
| Number of Macro Cells | 64 |
| JTAG BST | YES |
| Voltage Supply - Internal | 3V~3.6V |
| Height Seated (Max) | 1.2mm |
| Length | 7mm |
| Width | 7mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
LA4064V-75TN48E Overview
The mobile phone network has 64 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).48-TQFPis the package in which it resides.As a result, it has 32 I/O ports programmed.The termination of a device is set to [0].There is a QUADterminal position on the electrical part in question.It is powered by a voltage of 3.3V volts.The part belongs to Programmable Logic Devices family.It is recommended to package the chip by Tray.During operation, the operating temperature is kept at -40°C~125°C TA to ensure its reliability.Mount the chip by Surface Mount.In this case, it is a type of FPGA belonging to the LA-ispMACH series.A chip with 48pins is programmed.It is also possible to find YESwhen using this device.The LA4064can be used to identify its related parts.In this case, EEPROMwill be used to store the data.Surface Mountis the mounting point of this electronic part.The device has a pinout of [0].This device operates at a voltage of 3.6Vas its maximum supply voltage.With a minimal supply voltage of [0], it operates.It is possible to achieve a frequency of 168MHz.There are 4 logic blocks (LABs) in its basic building block.
LA4064V-75TN48E Features
48-TQFP package
32 I/Os
The operating temperature of -40°C~125°C TA
48 pin count
48 pins
4 logic blocks (LABs)
LA4064V-75TN48E Applications
There are a lot of Lattice Semiconductor Corporation LA4064V-75TN48E CPLDs applications.
- Address decoders
- ROM patching
- Interface bridging
- Dedicated input registers
- Custom shift registers
- Software-driven hardware configuration
- USB Bus
- Auxiliary Power Supply Isolated and Non-isolated
- DDC INTERFACE
- Pattern recognition
