LC5512MV-75F484I
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 484-BBGA |
| Number of Pins | 484 |
| Operating Temperature | -40°C~105°C TJ |
| Packaging | Tray |
| Published | 2000 |
| Series | ispXPLD® 5000MV |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 484 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | YES |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 225 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1mm |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | LC5512 |
| Pin Count | 484 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 3.3V |
| Programmable Type | In System Programmable |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Operating Supply Current | 33mA |
| Number of I/O | 253 |
| Nominal Supply Current | 33mA |
| Memory Type | EEPROM, SRAM |
| Propagation Delay | 9.5 ns |
| Max Frequency | 275MHz |
| Number of Programmable I/O | 100 |
| Output Function | MACROCELL |
| Number of Macro Cells | 512 |
| JTAG BST | YES |
| Voltage Supply - Internal | 3V~3.6V |
| Delay Time tpd(1) Max | 7.5ns |
| Number of Logic Elements/Blocks | 16 |
| Height Seated (Max) | 2.6mm |
| Length | 23mm |
| Width | 23mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Lead Free |
LC5512MV-75F484I Overview
512 macrocells are present in the mobile phone network, which offer radio coverage from a high-power cell tower, antenna, or mast.There is a 484-BBGA package containing it.In this case, there are 253 I/Os programmed.484terminations are programmed into the device.Its terminal position is BOTTOM.Power is supplied by a voltage of 3.3V volts.There is a part in the family [0].It is recommended that the chip be packaged by Tray.To ensure reliability, the device operates at a temperature of [0].Chips should be mounted by Surface Mount.It belongs to the ispXPLD? 5000MVseries of FPGAs.There are 484pins on the chip.Additionally, this device is capable of displaying [0].You can find its related parts in the [0].High efficiency requires a voltage supply of [0].It is recommended that data be stored in [0].The electronic component is mounted by Surface Mount.There are 484 pins on the device.A voltage of 3.6V is the maximum supply voltage for this device.It operates with the minimal supply voltage of 3V.There are 16 logic elements/blocks, which are fundamental building blocks of field-programmable gate array (FPGA) technology.There are a total of 100 Programmable I/Os.It is recommended that the maximal frequency be lower than 275MHz.
LC5512MV-75F484I Features
484-BBGA package
253 I/Os
The operating temperature of -40°C~105°C TJ
484 pin count
484 pins
LC5512MV-75F484I Applications
There are a lot of Lattice Semiconductor Corporation LC5512MV-75F484I CPLDs applications.
- Discrete logic functions
- SUPERVISORY FUNCTION (LVD AND WATCHDOG)
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- ANALOG-TO-DIGITAL CONVERTOR (ADC)
- PULSE WIDTH MODULATION (PWM)
- Code converters
- DDC INTERFACE
- USB Bus
- ON-CHIP OSCILLATOR CIRCUIT
- Multiple Clock Source Selection
