MC100EL30DWG
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2006 |
| Series | 100EL |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 20 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | ECL |
| Voltage - Supply | -4.2V~-5.7V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 100EL30 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.7V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 4.2V |
| Number of Circuits | 3 |
| Output Current | 50mA |
| Clock Frequency | 1.2GHz |
| Propagation Delay | 820 ps |
| Turn On Delay Time | 570 ps |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 62mA |
| Halogen Free | Halogen Free |
| Number of Bits per Element | 1 |
| Trigger Type | Positive Edge |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
MC100EL30DWG Overview
It is packaged in the way of 20-SOIC (0.295, 7.50mm Width). Package Tubeembeds it. There is a Differentialoutput configured with it. It is configured with a trigger that uses a value of Positive Edge. Surface Mountis positioned in the way of this electronic part. With a supply voltage of -4.2V~-5.7V volts, it operates. -40°C~85°C TAis the operating temperature. It belongs to the type D-Typeof flip flops. This type of FPGA is a part of the 100EL series. You should not exceed 1.2GHzin its output frequency. As a result, it consumes 62mA of quiescent current without being affected by external factors. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 100EL30 family contains this object. The power source is powered by 5V. There is an electronic part mounted in the way of Surface Mount. Basically, it is designed with a set of 20 pins. It has a clock edge trigger type of Positive Edge. The part is included in FF/Latches. It reaches 5.7Vwhen the supply voltage is maximal (Vsup). A normal operating voltage (Vsup) should remain above 4.2V. Due to its superior flexibility, it uses 3 circuits. In light of its reliable performance, this T flip flop is well suited for RAIL. In order for the device to operate, it requires -4.5V power supplies. The 50mA output current allows it to be designed with the greatest amount of flexibility. It is also characterized by NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V.
MC100EL30DWG Features
Tube package
100EL series
20 pins
-4.5V power supplies
MC100EL30DWG Applications
There are a lot of ON Semiconductor MC100EL30DWG Flip Flops applications.
- Frequency Divider circuits
- Data storage
- Pattern generators
- High Performance Logic for test systems
- Computing
- Data Synchronizers
- Power down protection
- Divide a clock signal by 2 or 4
- Memory
- 2 – Bit synchronous counter
