MC100EL35D
| Parameters | |
|---|---|
| Power Supplies | +-5V |
| Supply Voltage-Min (Vsup) | 4.2V |
| Number of Circuits | 1 |
| Number of Bits | 2 |
| Clock Frequency | 2.2GHz |
| Propagation Delay | 700 ps |
| Turn On Delay Time | 525 ps |
| Logic Function | Flip-Flop |
| Current - Quiescent (Iq) | 32mA |
| Output Characteristics | OPEN-EMITTER |
| Prop. Delay@Nom-Sup | 0.745 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | 50mA |
| Low Level Output Current | 50mA |
| Power Supply Current-Max (ICC) | 37mA |
| Clock Edge Trigger Type | Positive Edge |
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2008 |
| Series | 100EL |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | ECL |
| Voltage - Supply | -4.2V~-5.7V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 5V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100EL35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.7V |
MC100EL35D Overview
As a result, it is packaged as 8-SOIC (0.154, 3.90mm Width). Package Tubeembeds it. The output it is configured with uses Differential. The trigger it is configured with uses Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The supply voltage is set to -4.2V~-5.7V. It is operating at -40°C~85°C TA. This D latch has the type D-Type. In FPGA terms, D flip flop is a type of 100ELseries FPGA. Its output frequency should not exceed 2.2GHz. There is a consumption of 32mAof quiescent energy. A total of 8 terminations have been made. The 100EL35 family contains it. It is powered by a voltage of 5V . There is an electronic part that is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 8. This device exhibits a clock edge trigger type of Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. It is designed with 2bits. It reaches 5.7Vwhen the supply voltage is maximal (Vsup). For normal operation, the supply voltage (Vsup) should be kept above 4.2V. Its superior flexibility is attributed to its use of 1 circuits. As a result of its reliability, this D flip flop is ideally suited for RAIL. It operates from +-5V power supplies. NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7Vis also one of its characteristics. There is 50mA output current at the high level. It is set to 50mAfor low level output current.
MC100EL35D Features
Tube package
100EL series
8 pins
2 Bits
+-5V power supplies
MC100EL35D Applications
There are a lot of ON Semiconductor MC100EL35D Flip Flops applications.
- EMI reduction circuitry
- Clock pulse
- Data Synchronizers
- ATE
- Balanced 24 mA output drivers
- Frequency division
- Consumer
- Modulo – n – counter
- CMOS Process
- Latch-up performance
