MC100EL51D
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2008 |
| Series | 100EL |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | ECL |
| Voltage - Supply | -4.2V~-5.7V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100EL51 |
| Function | Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.7V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 4.2V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 2.8GHz |
| Propagation Delay | 565 ps |
| Turn On Delay Time | 475 ps |
| Logic Function | Flip-Flop |
| Current - Quiescent (Iq) | 29mA |
| Output Characteristics | OPEN-EMITTER |
| Prop. Delay@Nom-Sup | 0.62 ns |
| Trigger Type | Positive, Negative |
| Power Supply Current-Max (ICC) | 36mA |
| fmax-Min | 2200 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Length | 4.9mm |
| Width | 3.9mm |
| Radiation Hardening | No |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC100EL51D Overview
As a result, it is packaged as 8-SOIC (0.154, 3.90mm Width). The package Tubecontains it. It is configured with Differentialas an output. It is configured with a trigger that uses Positive, Negative. There is an electric part mounted in the way of Surface Mount. The JK flip flop operates at -4.2V~-5.7Vvolts. -40°C~85°C TAis the operating temperature. A flip flop of this type is classified as a D-Type. JK flip flop is a part of the 100ELseries of FPGAs. It should not exceed 2.8GHzin its output frequency. As a result, it consumes 29mA quiescent current. 8terminations have occurred. D latch belongs to the 100EL51 family. Power is provided by a 5V supply. The electronic part is mounted in the way of Surface Mount. A total of 8pins are provided on this board. A Positive Edgeclock edge trigger is used in this device. There is a FF/Latchesbase part number assigned to the RS flip flops. Flip flops designed with 1bits are used in this part. It reaches the maximum supply voltage (Vsup) at 5.7V. Normal operation requires a supply voltage (Vsup) above 4.2V. The superior flexibility of this circuit is achieved by using 1 circuits. Considering its reliability, this T flip flop is well suited for RAIL. An electrical current of -4.5V volts is applied to it. There is also a characteristic of NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V.
MC100EL51D Features
Tube package
100EL series
8 pins
1 Bits
-4.5V power supplies
MC100EL51D Applications
There are a lot of ON Semiconductor MC100EL51D Flip Flops applications.
- Single Up Count-Control Line
- Digital electronics systems
- Storage registers
- Latch
- ESD performance
- Shift registers
- Functionally equivalent to the MC10/100EL29
- 2 – Bit synchronous counter
- Control circuits
- Memory
