MC100EP31DR2
| Parameters | |
|---|---|
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100EP31 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 3GHz |
| Propagation Delay | 410 ps |
| Turn On Delay Time | 340 ps |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 45mA |
| Trigger Type | Positive Edge |
| Power Supply Current-Max (ICC) | 47mA |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2008 |
| Series | 100EP |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3.0V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
MC100EP31DR2 Overview
The item is packaged in 8-SOIC (0.154, 3.90mm Width)cases. It is included in the package Tape & Reel (TR). Currently, the output is configured to use Differential. The trigger it is configured with uses Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The supply voltage is set to -3V~-5.5V. It is at -40°C~85°C TAdegrees Celsius that the system is operating. A flip flop of this type is classified as a D-Type. In FPGA terms, D flip flop is a type of 100EPseries FPGA. Its output frequency should not exceed 3GHz Hz. During its operation, it consumes 45mA quiescent energy. The number of terminations is 8. If you search by 100EP31, you will find similar parts. A voltage of 3.3V is used to power it. Surface Mount mounts this electronic component. There are 8pins on it. In this device, the clock edge trigger type is Positive Edge. The RS flip flops belongs to FF/Latches base part number. There are 1bits in this flip flop. Vsup reaches 5.5V, the maximal supply voltage. The supply voltage (Vsup) should be kept above 3V for normal operation. 1 circuits are used to achieve its superior flexibility. A reliable performance of this D flip flop makes it well suited for use in TAPE AND REEL. The D latch runs on a voltage of -4.5V volts. Additionally, you may refer to the additional NECL MODE: VCC = 0V WITH VEE = -3.0V TO -5.5V of the electronic flip flop.
MC100EP31DR2 Features
Tape & Reel (TR) package
100EP series
8 pins
1 Bits
-4.5V power supplies
MC100EP31DR2 Applications
There are a lot of ON Semiconductor MC100EP31DR2 Flip Flops applications.
- Counters
- Pattern generators
- Memory
- Control circuits
- Storage registers
- Circuit Design
- Event Detectors
- Guaranteed simultaneous switching noise level
- Reduced system switching noise
- Divide a clock signal by 2 or 4
