Parameters |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
8-TSSOP, 8-MSOP (0.118, 3.00mm Width) |
Number of Pins |
8 |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tape & Reel (TR) |
Published |
2008 |
Series |
100EP |
JESD-609 Code |
e0 |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
8 |
Type |
D-Type |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Additional Feature |
NECL MODE: VCC = 0V WITH VEE = -3.0V TO -5.5V |
Subcategory |
FF/Latches |
Packing Method |
TAPE AND REEL |
Technology |
ECL |
Voltage - Supply |
-3V~-5.5V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
240 |
Supply Voltage |
3.3V |
Terminal Pitch |
0.65mm |
Reach Compliance Code |
not_compliant |
Time@Peak Reflow Temperature-Max (s) |
30 |
Base Part Number |
100EP31 |
Function |
Set(Preset) and Reset |
Qualification Status |
Not Qualified |
Output Type |
Differential |
Polarity |
Non-Inverting |
Supply Voltage-Max (Vsup) |
5.5V |
Power Supplies |
-4.5V |
Supply Voltage-Min (Vsup) |
3V |
Number of Circuits |
1 |
Number of Bits |
1 |
Clock Frequency |
3GHz |
Propagation Delay |
410 ps |
Turn On Delay Time |
340 ps |
Logic Function |
AND, D-Type, Flip-Flop |
Current - Quiescent (Iq) |
45mA |
Trigger Type |
Positive Edge |
High Level Output Current |
50mA |
Low Level Output Current |
50mA |
Power Supply Current-Max (ICC) |
47mA |
Clock Edge Trigger Type |
Positive Edge |
Max Frequency@Nom-Sup |
3000000000Hz |
Length |
3mm |
Width |
3mm |
RoHS Status |
Non-RoHS Compliant |
Lead Free |
Contains Lead |
MC100EP31DTR2 Overview
8-TSSOP, 8-MSOP (0.118, 3.00mm Width)is the way it is packaged. D flip flop is embedded in the Tape & Reel (TR) package. It is configured with Differentialas an output. In the configuration of the trigger, Positive Edgeis used. Surface Mountis occupied by this electronic component. It operates with a supply voltage of -3V~-5.5V. The operating temperature is -40°C~85°C TA. It belongs to the type D-Typeof flip flops. JK flip flop belongs to the 100EPseries of FPGAs. There should be no greater frequency than 3GHzon its output. Despite external influences, it consumes 45mAof quiescent current. There are 8 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The 100EP31 family contains this object. An input voltage of 3.3Vpowers the D latch. The electronic part is mounted in the way of Surface Mount. It is designed with 8 pins. This device's clock edge trigger type is Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. The flip flop is designed with 1bits. It reaches 5.5Vwhen the maximum supply voltage (Vsup) is applied. Keeping the supply voltage (Vsup) above 3V is necessary for normal operation. Despite its superior flexibility, it relies on 1 circuits to achieve it. As a result of its reliability, this D flip flop is ideally suited for TAPE AND REEL. A total of -4.5V power supplies are needed to run it. In addition, you can refer to the additinal NECL MODE: VCC = 0V WITH VEE = -3.0V TO -5.5V of the D latch. High level output current is set to 50mA. A 50mAvalue is set for low-level output current.
MC100EP31DTR2 Features
Tape & Reel (TR) package
100EP series
8 pins
1 Bits
-4.5V power supplies
MC100EP31DTR2 Applications
There are a lot of ON Semiconductor MC100EP31DTR2 Flip Flops applications.
- Latch-up performance
- Data Synchronizers
- Parallel data storage
- Shift registers
- Convert a momentary switch to a toggle switch
- Memory
- Divide a clock signal by 2 or 4
- Differential Individual
- Test & Measurement
- CMOS Process