MC100EP35DG
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | LIFETIME (Last Updated: 1 month ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2000 |
| Series | 100EP |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | Tin (Sn) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 100EP35 |
| Function | Reset |
| Output Type | Differential |
| Operating Supply Voltage | 4.25V |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Output Current | 50mA |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 575 ps |
| Turn On Delay Time | 410 ps |
| Logic Function | Flip-Flop, JK-Type, NOR, OR |
| Halogen Free | Halogen Free |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 4.9mm |
| Width | 3.9mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
MC100EP35DG Overview
The flip flop is packaged in a case of 8-SOIC (0.154, 3.90mm Width). The Tubepackage contains it. As configured, the output uses Differential. The trigger configured with it uses Positive Edge. Surface Mountis occupied by this electronic component. A voltage of -3V~-5.5Vis required for its operation. Temperature is set to -40°C~85°C TA. There is JK Type type of electronic flip flop associated with this device. In this case, it is a type of FPGA belonging to the 100EP series. In order for it to function properly, its output frequency should not exceed 3GHz. A total of 8 terminations have been made. This D latch belongs to the family of 100EP35. The D flip flop is powered by a voltage of 3.3V . There is an electronic component mounted in the way of Surface Mount. The electronic flip flop is designed with pins 8. This device's clock edge trigger type is Positive Edge. The part you are looking for is included in FF/Latches. This flip flop is designed with 2 Bits. 5.5Vis the maximum supply voltage (Vsup). For normal operation, the supply voltage (Vsup) should be kept above 3V. Considering its reliability, this T flip flop is well suited for RAIL. The D latch operates on -4.5V volts. If high efficiency is to be achieved, the supply voltage should be maintained at 4.25V. With a current output of 50mA , it offers maximum design flexibility. In order for the chip to function, it has 1output lines. Additionally, you may refer to the D latch's additional NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V. In this case, the high level output current is set to -50mA. There is 50mA output current at the low level.
MC100EP35DG Features
Tube package
100EP series
8 pins
2 Bits
-4.5V power supplies
MC100EP35DG Applications
There are a lot of ON Semiconductor MC100EP35DG Flip Flops applications.
- High Performance Logic for test systems
- Functionally equivalent to the MC10/100EL29
- Pattern generators
- Data storage
- Convert a momentary switch to a toggle switch
- Buffer registers
- Circuit Design
- Latch
- Bus hold
- Matched Rise and Fall
