MC100EP35DR2
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2008 |
| Series | 100EP |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100EP35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 490 ps |
| Turn On Delay Time | 410 ps |
| Logic Function | Flip-Flop |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC100EP35DR2 Overview
8-SOIC (0.154, 3.90mm Width)is the packaging method. A package named Tape & Reel (TR)includes it. The output it is configured with uses Differential. This trigger uses the value Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. A -3V~-5.5Vsupply voltage is required for it to operate. A temperature of -40°C~85°C TAis considered to be the operating temperature. There is JK Type type of electronic flip flop associated with this device. The 100EPseries comprises this type of FPGA. In order for it to function properly, its output frequency should not exceed 3GHz. In 8terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The object belongs to the 100EP35 family. Power is provided by a 3.3V supply. The electronic part is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 8. This device's clock edge trigger type is Positive Edge. This device has the base part number FF/Latches. An electronic part with 2bits has been designed. It reaches 5.5Vwhen the maximum supply voltage (Vsup) is applied. For normal operation, the supply voltage (Vsup) should be above 3V. As a result of its reliability, this D flip flop is ideally suited for TAPE AND REEL. The D latch runs on a voltage of -4.5V volts. There are no output lines on the JK flip flop. In addition, you can refer to the additinal NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V of the D latch. The high level output current is set to -50mA. There is no low level output current set at 50mA.
MC100EP35DR2 Features
Tape & Reel (TR) package
100EP series
8 pins
2 Bits
-4.5V power supplies
MC100EP35DR2 Applications
There are a lot of ON Semiconductor MC100EP35DR2 Flip Flops applications.
- Automotive
- Single Down Count-Control Line
- Differential Individual
- Parallel data storage
- Pattern generators
- Dynamic threshold performance
- Clock pulse
- Load Control
- ESD performance
- Consumer
