MC100EP35DR2G
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2008 |
| Series | 100EP |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | Tin (Sn) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 100EP35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 490 ps |
| Turn On Delay Time | 410 ps |
| Logic Function | Flip-Flop, JK-Type |
| Halogen Free | Halogen Free |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
MC100EP35DR2G Overview
It is packaged in the way of 8-SOIC (0.154, 3.90mm Width). The package Tape & Reel (TR)contains it. T flip flop is configured with an output of Differential. The trigger configured with it uses Positive Edge. Surface Mountis in the way of this electric part. The JK flip flop operates at -3V~-5.5Vvolts. Temperature is set to -40°C~85°C TA. Logic flip flops of this type are classified as JK Type. In this case, it is a type of FPGA belonging to the 100EP series. You should not exceed 3GHzin the output frequency of the device. Terminations are 8. If you search by 100EP35, you will find similar parts. It is powered by a voltage of 3.3V . It is mounted by the way of Surface Mount. The electronic flip flop is designed with pins 8. It has a clock edge trigger type of Positive Edge. It is part of the FF/Latchesbase part number family. There are 2bits in its design. In this case, the maximum supply voltage (Vsup) reaches 5.5V. It is imperative that the supply voltage (Vsup) is maintained above 3Vin order to ensure normal operation. Considering its reliability, this T flip flop is well suited for TAPE AND REEL. A total of -4.5V power supplies are needed to run it. To operate, the chip has a total of 1 output lines. Additionally, you may refer to the additional NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V of the electronic flip flop. In this case, the high level output current is set to -50mA. There is no low level output current set at 50mA.
MC100EP35DR2G Features
Tape & Reel (TR) package
100EP series
8 pins
2 Bits
-4.5V power supplies
MC100EP35DR2G Applications
There are a lot of ON Semiconductor MC100EP35DR2G Flip Flops applications.
- ESD performance
- Latch
- Balanced Propagation Delays
- ESCC
- Reduced system switching noise
- ESD protection
- Matched Rise and Fall
- Divide a clock signal by 2 or 4
- Pattern generators
- Buffer registers
