MC100EP35DT
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-TSSOP, 8-MSOP (0.118, 3.00mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2008 |
| Series | 100EP |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100EP35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 490 ps |
| Turn On Delay Time | 410 ps |
| Logic Function | Flip-Flop |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 3mm |
| Width | 3mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC100EP35DT Overview
The item is packaged in 8-TSSOP, 8-MSOP (0.118, 3.00mm Width)cases. The package Tubecontains it. This output is configured with Differential. This trigger is configured to use Positive Edge. Surface Mountis occupied by this electronic component. The supply voltage is set to -3V~-5.5V. In the operating environment, the temperature is -40°C~85°C TA. Logic flip flops of this type are classified as JK Type. In FPGA terms, D flip flop is a type of 100EPseries FPGA. It should not exceed 3GHzin terms of its output frequency. There have been 8 terminations. The 100EP35 family contains this object. Power is supplied from a voltage of 3.3V volts. Surface Mount mounts this electronic component. This board is designed with 8pins on it. This device has the clock edge trigger type of Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. There are 2bits in its design. 5.5Vis the maximum supply voltage (Vsup). If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 3V. As a result of its reliability, this D flip flop is ideally suited for RAIL. The D latch operates on -4.5V volts. In order to operate, the chip has 1 output lines. In addition, NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5Vis a characteristic of it. A high level output current of -50mAis set. The low level output current is set to 50mA.
MC100EP35DT Features
Tube package
100EP series
8 pins
2 Bits
-4.5V power supplies
MC100EP35DT Applications
There are a lot of ON Semiconductor MC100EP35DT Flip Flops applications.
- EMI reduction circuitry
- Latch
- Frequency Divider circuits
- Pattern generators
- Buffered Clock
- Computers
- Clock pulse
- Registers
- ATE
- Circuit Design
