MC100EP35MNR4G
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 8-VFDFN Exposed Pad |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 100EP |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | MATTE TIN |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| JESD-30 Code | S-XDSO-N8 |
| Function | Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Differential |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Current - Quiescent (Iq) | 50mA |
| Output Polarity | COMPLEMENTARY |
| Trigger Type | Positive Edge |
| Propagation Delay (tpd) | 0.49 ns |
| Length | 2mm |
| Width | 2mm |
| RoHS Status | ROHS3 Compliant |
MC100EP35MNR4G Overview
In the form of 8-VFDFN Exposed Pad, it has been packaged. A package named Tape & Reel (TR)includes it. Differentialis the output configured for it. In the configuration of the trigger, Positive Edgeis used. Surface Mountis positioned in the way of this electronic part. The JK flip flop operates at a voltage of -3V~-5.5V. In the operating environment, the temperature is -40°C~85°C TA. A flip flop of this type is classified as a JK Type. FPGAs belonging to the 100EPseries contain this type of chip. You should not exceed 3GHzin its output frequency. A total of 1elements are present in it. T flip flop consumes 50mA quiescent energy. In 8terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. A voltage of 3.3V is used to power it. This flip flop is designed with 2 Bits. As soon as 5.5Vis reached, Vsup reaches its maximum value. Normally, the supply voltage (Vsup) should be kept above 3V. It is also characterized by NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V.
MC100EP35MNR4G Features
Tape & Reel (TR) package
100EP series
2 Bits
MC100EP35MNR4G Applications
There are a lot of Rochester Electronics, LLC MC100EP35MNR4G Flip Flops applications.
- Modulo – n – counter
- Power down protection
- Divide a clock signal by 2 or 4
- Count Modes
- Communications
- Consumer
- Frequency Divider circuits
- Counters
- ESD protection
- Buffered Clock
