MC100LVEL29DWR2G
| Parameters | |
|---|---|
| Series | 100LVEL |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | 3V~3.8V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 100LVEL29 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.8V |
| Power Supplies | -3.3V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 2 |
| Clock Frequency | 1.1GHz |
| Propagation Delay | 700 ps |
| Turn On Delay Time | 740 ps |
| Logic Function | D-Type, Flip-Flop |
| Output Characteristics | OPEN-EMITTER |
| Halogen Free | Halogen Free |
| Number of Bits per Element | 1 |
| Trigger Type | Positive Edge |
| Clock Edge Trigger Type | Positive Edge |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 2 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Number of Pins | 20 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 1997 |
MC100LVEL29DWR2G Overview
20-SOIC (0.295, 7.50mm Width)is the way it is packaged. There is an embedded version in the package Tape & Reel (TR). The output it is configured with uses Differential. Positive Edgeis the trigger it is configured with. Surface Mountis occupied by this electronic component. A 3V~3.8Vsupply voltage is required for it to operate. It is at -40°C~85°C TAdegrees Celsius that the system is operating. Logic flip flops of this type are classified as D-Type. In terms of FPGAs, it belongs to the 100LVEL series. There should be no greater frequency than 1.1GHzon its output. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. This D latch belongs to the family of 100LVEL29. A voltage of 3.3V is used as the power supply for this D latch. In this case, the electronic component is mounted in the way of Surface Mount. The electronic flip flop is designed with pins 20. The clock edge trigger type for this device is Positive Edge. This device has the base part number FF/Latches. As soon as 3.8Vis reached, Vsup reaches its maximum value. It is imperative that the supply voltage (Vsup) is maintained above 3Vin order to ensure normal operation. Using 2 circuits, it is highly flexible. As a result of its reliable performance, this T flip flop is suitable for TAPE AND REEL. A power supply of -3.3Vis required to operate it. NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8Vis also one of its characteristics.
MC100LVEL29DWR2G Features
Tape & Reel (TR) package
100LVEL series
20 pins
-3.3V power supplies
MC100LVEL29DWR2G Applications
There are a lot of ON Semiconductor MC100LVEL29DWR2G Flip Flops applications.
- Instrumentation
- Data storage
- EMI reduction circuitry
- Memory
- Supports Live Insertion
- High Performance Logic for test systems
- Differential Individual
- Consumer
- Modulo – n – counter
- Clock pulse
