MC100LVEL31DR2G
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2000 |
| Series | 100LVEL |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -3V~-3.8V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 100LVEL31 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Power Supplies | -3.3V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 2.9GHz |
| Propagation Delay | 590 ps |
| Turn On Delay Time | 475 ps |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 35mA |
| Output Characteristics | OPEN-EMITTER |
| Halogen Free | Halogen Free |
| Trigger Type | Positive Edge |
| fmax-Min | 2900 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 2900000000Hz |
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
MC100LVEL31DR2G Overview
The item is packaged in 8-SOIC (0.154, 3.90mm Width)cases. There is an embedded version in the package Tape & Reel (TR). The output it is configured with uses Differential. In the configuration of the trigger, Positive Edgeis used. The electronic part is mounted in the way of Surface Mount. A supply voltage of -3V~-3.8V is required for operation. In the operating environment, the temperature is -40°C~85°C TA. It is an electronic flip flop with the type D-Type. JK flip flop is a part of the 100LVELseries of FPGAs. This D flip flop should not have a frequency greater than 2.9GHz. This process consumes 35mA quiescents. A total of 8 terminations have been made. The 100LVEL31 family contains it. It is powered from a supply voltage of 3.3V. There is an electronic part that is mounted in the way of Surface Mount. This board has 8 pins. There is a clock edge trigger type of Positive Edgeon this device. The RS flip flops belongs to FF/Latches base part number. 1bits are used in its design. Keeping the supply voltage (Vsup) above 3V is necessary for normal operation. The superior flexibility is achieved through the use of 1 circuits. As a result of its reliable performance, this T flip flop is suitable for TAPE AND REEL. The system runs on a power supply of -3.3V watts.
MC100LVEL31DR2G Features
Tape & Reel (TR) package
100LVEL series
8 pins
1 Bits
-3.3V power supplies
MC100LVEL31DR2G Applications
There are a lot of ON Semiconductor MC100LVEL31DR2G Flip Flops applications.
- CMOS Process
- Storage Registers
- Single Down Count-Control Line
- Instrumentation
- Automotive
- Memory
- Storage registers
- Latch-up performance
- Single Up Count-Control Line
- Modulo – n – counter
