MC100LVEL31DT
| Parameters | |
|---|---|
| fmax-Min | 2900 MHz |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 2900000000Hz |
| Length | 3mm |
| Width | 3mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-TSSOP, 8-MSOP (0.118, 3.00mm Width) |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2008 |
| Series | 100LVEL |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | ECL |
| Voltage - Supply | -3V~-3.8V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 100LVEL31 |
| JESD-30 Code | S-PDSO-G8 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.8V |
| Power Supplies | -4.5V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 1 |
| Number of Bits | 1 |
| Clock Frequency | 2.9GHz |
| Propagation Delay | 590 ps |
| Turn On Delay Time | 475 ps |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 35mA |
| Trigger Type | Positive Edge |
| Power Supply Current-Max (ICC) | 38mA |
MC100LVEL31DT Overview
In the form of 8-TSSOP, 8-MSOP (0.118, 3.00mm Width), it has been packaged. Package Tubeembeds it. T flip flop is configured with an output of Differential. There is a trigger configured with Positive Edge. It is mounted in the way of Surface Mount. A voltage of -3V~-3.8Vis required for its operation. A temperature of -40°C~85°C TAis used in the operation. This D latch has the type D-Type. The 100LVELseries comprises this type of FPGA. In order for it to function properly, its output frequency should not exceed 2.9GHz. It consumes 35mA of quiescent current without being affected by external factors. Terminations are 8. Members of the 100LVEL31family make up this object. The D flip flop is powered by a voltage of 3.3V . It is mounted by the way of Surface Mount. This device's clock edge trigger type is Positive Edge. The part you are looking for is included in FF/Latches. An electronic part designed with 1bits is used in this application. It reaches 3.8Vwhen the maximum supply voltage (Vsup) is applied. For normal operation, the supply voltage (Vsup) should be kept above 3V. Due to its superior flexibility, it uses 1 circuits. Compared to other similar T flip flops, this device offers reliable performance and is well suited for RAIL. A total of -4.5V power supplies are needed to run it. Additionally, you may refer to the additional NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V of the electronic flip flop.
MC100LVEL31DT Features
Tube package
100LVEL series
1 Bits
-4.5V power supplies
MC100LVEL31DT Applications
There are a lot of ON Semiconductor MC100LVEL31DT Flip Flops applications.
- Memory
- Bounce elimination switch
- Balanced 24 mA output drivers
- Single Down Count-Control Line
- Instrumentation
- Counters
- Latch-up performance
- Consumer
- Event Detectors
- Set-reset capability
