MC10E431FN
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 28-LCC (J-Lead) |
| Number of Pins | 28 |
| Operating Temperature | 0°C~85°C TA |
| Packaging | Tube |
| Published | 1996 |
| Series | 10E |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 28 |
| Type | D-Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V |
| Subcategory | FF/Latches |
| Technology | ECL |
| Voltage - Supply | -4.2V~-5.7V |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 5V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 10E431 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.7V |
| Power Supplies | -5.2V |
| Supply Voltage-Min (Vsup) | 4.2V |
| Clock Frequency | 1.1GHz |
| Propagation Delay | 850 ps |
| Turn On Delay Time | 700 ps |
| Family | 10E |
| Logic Function | AND, Flip-Flop |
| Current - Quiescent (Iq) | 132mA |
| Output Characteristics | OPEN-EMITTER |
| Number of Bits per Element | 1 |
| Trigger Type | Positive, Negative |
| Number of Input Lines | 3 |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 4.57mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC10E431FN Overview
The flip flop is packaged in 28-LCC (J-Lead). You can find it in the Tubepackage. As configured, the output uses Differential. There is a trigger configured with Positive, Negative. It is mounted in the way of Surface Mount. The JK flip flop operates at -4.2V~-5.7Vvolts. In this case, the operating temperature is 0°C~85°C TA. It is an electronic flip flop with the type D-Type. It belongs to the 10Eseries of FPGAs. There should be no greater frequency than 1.1GHzon its output. This process consumes 132mA quiescents. Currently, there are 28 terminations. JK flip flop belongs to 10E431 family. A voltage of 5V is used as the power supply for this D latch. 10Eis the family of this D flip flop. The electronic part is mounted in the way of Surface Mount. A total of 28pins are provided on this board. A Positive Edgeclock edge trigger is used in this device. There is a base part number FF/Latchesfor the RS flip flops. It reaches 5.7Vwhen the maximum supply voltage (Vsup) is applied. A normal operating voltage (Vsup) should remain above 4.2V. In order for the device to operate, it requires -5.2V power supplies. 3input lines are available for you to choose from. NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7Vis also one of its characteristics.
MC10E431FN Features
Tube package
10E series
28 pins
-5.2V power supplies
MC10E431FN Applications
There are a lot of ON Semiconductor MC10E431FN Flip Flops applications.
- Data Synchronizers
- Buffered Clock
- Automotive
- Clock pulse
- Digital electronics systems
- Matched Rise and Fall
- Divide a clock signal by 2 or 4
- Balanced Propagation Delays
- Reduced system switching noise
- EMI reduction circuitry
