Parameters |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
8-TSSOP, 8-MSOP (0.118, 3.00mm Width) |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tube |
Published |
2008 |
Series |
10EL |
JESD-609 Code |
e0 |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
8 |
Type |
D-Type |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Additional Feature |
NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V |
Subcategory |
FF/Latches |
Packing Method |
RAIL |
Technology |
ECL |
Voltage - Supply |
-4.2V~-5.7V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
240 |
Supply Voltage |
5V |
Terminal Pitch |
0.65mm |
Reach Compliance Code |
not_compliant |
Time@Peak Reflow Temperature-Max (s) |
30 |
Base Part Number |
10EL51 |
JESD-30 Code |
S-PDSO-G8 |
Function |
Reset |
Qualification Status |
Not Qualified |
Output Type |
Differential |
Polarity |
Non-Inverting |
Supply Voltage-Max (Vsup) |
5.7V |
Power Supplies |
-5.2V |
Supply Voltage-Min (Vsup) |
4.2V |
Number of Circuits |
1 |
Number of Bits |
1 |
Clock Frequency |
2.8GHz |
Propagation Delay |
565 ps |
Turn On Delay Time |
475 ps |
Logic Function |
Flip-Flop |
Current - Quiescent (Iq) |
29mA |
Prop. Delay@Nom-Sup |
0.62 ns |
Trigger Type |
Positive, Negative |
Power Supply Current-Max (ICC) |
29mA |
fmax-Min |
2200 MHz |
Clock Edge Trigger Type |
Positive Edge |
Max Frequency@Nom-Sup |
2200000000Hz |
Length |
3mm |
Width |
3mm |
RoHS Status |
Non-RoHS Compliant |
Lead Free |
Contains Lead |
MC10EL51DT Overview
The flip flop is packaged in 8-TSSOP, 8-MSOP (0.118, 3.00mm Width). D flip flop is included in the Tubepackage. T flip flop is configured with an output of Differential. It is configured with a trigger that uses a value of Positive, Negative. There is an electric part mounted in the way of Surface Mount. A voltage of -4.2V~-5.7Vis used as the supply voltage. Temperature is set to -40°C~85°C TA. There is D-Type type of electronic flip flop associated with this device. JK flip flop is a part of the 10ELseries of FPGAs. There should be no greater frequency than 2.8GHzon its output. As a result, it consumes 29mA of quiescent current without being affected by external factors. There are 8 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. Members of the 10EL51family make up this object. A voltage of 5V is used as the power supply for this D latch. It is mounted in the way of Surface Mount. Its clock edge trigger type is Positive Edge. It is included in FF/Latches. It is designed with 1bits. The maximal supply voltage (Vsup) reaches 5.7V. For normal operation, the supply voltage (Vsup) should be kept above 4.2V. Its flexibility is enhanced by 1 circuits. In view of its reliability, this D flip flop is a good fit for RAIL. A power supply of -5.2Vis required to operate it. It is also characterized by NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V.
MC10EL51DT Features
Tube package
10EL series
1 Bits
-5.2V power supplies
MC10EL51DT Applications
There are a lot of ON Semiconductor MC10EL51DT Flip Flops applications.
- Bus hold
- Control circuits
- Memory
- Clock pulse
- Count Modes
- Event Detectors
- Reduced system switching noise
- Data Synchronizers
- Automotive
- Load Control