MC10EP131FAR2
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 32-LQFP |
| Number of Pins | 32 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Published | 2006 |
| Series | 10EP |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 32 |
| Type | D-Type |
| Terminal Finish | Tin/Lead (Sn80Pb20) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | 3V~5.5V |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.8mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 10EP131 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -5.2V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 4 |
| Number of Bits | 4 |
| Clock Frequency | 3GHz |
| Propagation Delay | 600 ps |
| Turn On Delay Time | 460 ps |
| Family | 10E |
| Logic Function | AND, Flip-Flop |
| Trigger Type | Positive Edge |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 7mm |
| Width | 7mm |
| Radiation Hardening | No |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC10EP131FAR2 Overview
In the form of 32-LQFP, it has been packaged. The package Cut Tape (CT)contains it. Differentialis the output configured for it. It is configured with a trigger that uses a value of Positive Edge. There is an electric part mounted in the way of Surface Mount. A supply voltage of 3V~5.5V is required for operation. In this case, the operating temperature is -40°C~85°C TA. This logic flip flop is classified as type D-Type. It is a type of FPGA belonging to the 10EP series. It should not exceed 3GHzin its output frequency. There are 1 elements in it. There are 32 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. This D latch belongs to the family of 10EP131. A voltage of 3.3V is used as the power supply for this D latch. The electronic device belongs to the 10Efamily. There is an electronic component mounted in the way of Surface Mount. Basically, it is designed with a set of 32 pins. A Positive Edgeclock edge trigger is used in this device. This part is included in FF/Latches. Flip flops designed with 4bits are used in this part. 5.5Vis the maximum supply voltage (Vsup). Keeping the supply voltage (Vsup) above 3V is necessary for normal operation. Its superior flexibility is attributed to its use of 4 circuits. A reliable performance of this D flip flop makes it well suited for use in TAPE AND REEL. In order for the device to operate, it requires -5.2V power supplies. As an additional reference, you may refer to electronic flip flop NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V.
MC10EP131FAR2 Features
Cut Tape (CT) package
10EP series
32 pins
4 Bits
-5.2V power supplies
MC10EP131FAR2 Applications
There are a lot of ON Semiconductor MC10EP131FAR2 Flip Flops applications.
- High Performance Logic for test systems
- Parallel data storage
- Synchronous counter
- Count Modes
- Frequency Divider circuits
- Bounce elimination switch
- ATE
- Bus hold
- Patented noise
- Storage registers
