MC10EP131MNG
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 32-VFQFN Exposed Pad |
| Number of Pins | 32 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2006 |
| Series | 10EP |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 32 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | TRAY |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 10EP131 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -5.2V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 4 |
| Clock Frequency | 3GHz |
| Propagation Delay | 600 ps |
| Turn On Delay Time | 460 ps |
| Family | 10E |
| Logic Function | AND |
| Current - Quiescent (Iq) | 120mA |
| Halogen Free | Halogen Free |
| Trigger Type | Positive, Negative |
| Number of Input Lines | 4 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 5mm |
| Width | 5mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
MC10EP131MNG Overview
In the form of 32-VFQFN Exposed Pad, it has been packaged. As part of the package Tube, it is embedded. Differentialis the output configured for it. It is configured with a trigger that uses a value of Positive, Negative. Surface Mountis in the way of this electric part. A voltage of -3V~-5.5Vis used as the supply voltage. -40°C~85°C TAis the operating temperature. This D latch has the type D-Type. FPGAs belonging to the 10EPseries contain this type of chip. A frequency of 3GHzshould be the maximum output frequency. In total, it contains 1 elements. As a result, it consumes 120mA of quiescent current without being affected by external factors. There are 32 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. D latch belongs to the 10EP131 family. Power is provided by a 3.3V supply. An electronic device belonging to the family 10Ecan be found here. The electronic part is mounted in the way of Surface Mount. It is designed with 32 pins. A Positive Edgeclock edge trigger is used in this device. This part is included in FF/Latches. There are 4bits in this flip flop. As soon as 5.5Vis reached, Vsup reaches its maximum value. The supply voltage (Vsup) should be maintained above 3V for normal operation. In view of its reliability, this D flip flop is a good fit for TRAY. The D latch runs on a voltage of -5.2V volts. The number of input lines is 4. It is also characterized by NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V.
MC10EP131MNG Features
Tube package
10EP series
32 pins
4 Bits
-5.2V power supplies
MC10EP131MNG Applications
There are a lot of ON Semiconductor MC10EP131MNG Flip Flops applications.
- Matched Rise and Fall
- Frequency Divider circuits
- Frequency Dividers
- Guaranteed simultaneous switching noise level
- Power down protection
- Divide a clock signal by 2 or 4
- Pattern generators
- Memory
- Single Down Count-Control Line
- Frequency division
