MC10EP131MNR4G
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 32-VFQFN Exposed Pad |
| Number of Pins | 32 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2006 |
| Series | 10EP |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 32 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 10EP131 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -5.2V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 4 |
| Clock Frequency | 3GHz |
| Propagation Delay | 600 ps |
| Turn On Delay Time | 460 ps |
| Family | 10E |
| Logic Function | AND |
| Current - Quiescent (Iq) | 120mA |
| Halogen Free | Halogen Free |
| Trigger Type | Positive, Negative |
| Number of Input Lines | 4 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 5mm |
| Width | 5mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
MC10EP131MNR4G Overview
32-VFQFN Exposed Padis the way it is packaged. D flip flop is embedded in the Tape & Reel (TR) package. As configured, the output uses Differential. It is configured with a trigger that uses a value of Positive, Negative. There is an electrical part that is mounted in the way of Surface Mount. A voltage of -3V~-5.5Vis required for its operation. Currently, the operating temperature is -40°C~85°C TA. This D latch has the type D-Type. JK flip flop belongs to the 10EPseries of FPGAs. Its output frequency should not exceed 3GHz Hz. A total of 1 elements are present. As a result, it consumes 120mA quiescent current. A total of 32 terminations have been made. This D latch belongs to the family of 10EP131. An input voltage of 3.3Vpowers the D latch. Devices in the 10Efamily are electronic devices. There is an electronic component mounted in the way of Surface Mount. The 32pins are designed into the board. In this device, the clock edge trigger type is Positive Edge. It is included in FF/Latches. 4bits are used in its design. It reaches 5.5Vwhen the supply voltage is maximal (Vsup). A normal operating voltage (Vsup) should remain above 3V. The power supply is -5.2V. It is reported that there are 4 input lines. There is also a characteristic of NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V.
MC10EP131MNR4G Features
Tape & Reel (TR) package
10EP series
32 pins
4 Bits
-5.2V power supplies
MC10EP131MNR4G Applications
There are a lot of ON Semiconductor MC10EP131MNR4G Flip Flops applications.
- Power down protection
- Dynamic threshold performance
- Frequency Divider circuits
- Computing
- Asynchronous counter
- Frequency Dividers
- QML qualified product
- Load Control
- Single Up Count-Control Line
- Memory
