MC10EP35D
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2008 |
| Series | 10EP |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 10EP35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -5.2V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 490 ps |
| Turn On Delay Time | 410 ps |
| Family | 10E |
| Logic Function | Flip-Flop |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC10EP35D Overview
The item is packaged in 8-SOIC (0.154, 3.90mm Width)cases. D flip flop is embedded in the Tube package. T flip flop uses Differentialas its output configuration. The trigger configured with it uses Positive Edge. There is an electronic component mounted in the way of Surface Mount. The supply voltage is set to -3V~-5.5V. -40°C~85°C TAis the operating temperature. The type of this D latch is JK Type. In this case, it is a type of FPGA belonging to the 10EP series. You should not exceed 3GHzin the output frequency of the device. The number of terminations is 8. D latch belongs to the 10EP35 family. A voltage of 3.3V is used as the power supply for this D latch. It belongs to the family of electronic devices known as 10E. There is an electronic part that is mounted in the way of Surface Mount. It is designed with 8 pins. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. This RS flip flops is a part number FF/Latches. 2bits are used in its design. It reaches 5.5Vwhen the supply voltage is maximal (Vsup). A normal operating voltage (Vsup) should remain above 3V. In light of its reliable performance, this T flip flop is well suited for RAIL. It operates from -5.2V power supplies. It has 1 output lines to operate. NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5Vis also one of its characteristics. High level output current is set to -50mA. 50mAis set as the low level output current.
MC10EP35D Features
Tube package
10EP series
8 pins
2 Bits
-5.2V power supplies
MC10EP35D Applications
There are a lot of ON Semiconductor MC10EP35D Flip Flops applications.
- Cold spare funcion
- Count Modes
- Storage Registers
- Frequency Dividers
- Memory
- Supports Live Insertion
- Buffer registers
- Computers
- Safety Clamp
- Individual Asynchronous Resets
