MC10EP35DG
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2008 |
| Series | 10EP |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | Tin (Sn) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 10EP35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -5.2V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 490 ps |
| Turn On Delay Time | 410 ps |
| Family | 10E |
| Logic Function | Flip-Flop, JK-Type |
| Halogen Free | Halogen Free |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
MC10EP35DG Overview
It is packaged in the way of 8-SOIC (0.154, 3.90mm Width). It is contained within the Tubepackage. The output it is configured with uses Differential. JK flip flop uses Positive Edgeas the trigger. The electronic part is mounted in the way of Surface Mount. It operates with a supply voltage of -3V~-5.5V. In the operating environment, the temperature is -40°C~85°C TA. The type of this D latch is JK Type. FPGAs belonging to the 10EPseries contain this type of chip. You should not exceed 3GHzin the output frequency of the device. A total of 8terminations have been recorded. JK flip flop belongs to 10EP35 family. It is powered by a voltage of 3.3V . Electronic devices of this type belong to the 10Efamily. It is mounted by the way of Surface Mount. The electronic flip flop is designed with pins 8. This device has the clock edge trigger type of Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. It is designed with a number of bits of 2. Vsup reaches 5.5V, the maximal supply voltage. Keeping the supply voltage (Vsup) above 3V is necessary for normal operation. In view of its reliability, this D flip flop is a good fit for RAIL. The system runs on a power supply of -5.2V watts. There are 1 output lines on it. Additionally, it is characterized by NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V. In this case, the high level output current is set to -50mA. It is set to 50mAfor the low level output current.
MC10EP35DG Features
Tube package
10EP series
8 pins
2 Bits
-5.2V power supplies
MC10EP35DG Applications
There are a lot of ON Semiconductor MC10EP35DG Flip Flops applications.
- Memory
- ESD performance
- Dynamic threshold performance
- Shift registers
- Count Modes
- Digital electronics systems
- Storage Registers
- Frequency division
- Bus hold
- Memory
