MC10EP35DTR2
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-TSSOP, 8-MSOP (0.118, 3.00mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2008 |
| Series | 10EP |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 10EP35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -5.2V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 490 ps |
| Turn On Delay Time | 410 ps |
| Family | 10E |
| Logic Function | Flip-Flop |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 3mm |
| Width | 3mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC10EP35DTR2 Overview
It is packaged in the way of 8-TSSOP, 8-MSOP (0.118, 3.00mm Width). There is an embedded version in the package Tape & Reel (TR). T flip flop uses Differentialas its output configuration. JK flip flop uses Positive Edgeas the trigger. There is an electric part mounted in the way of Surface Mount. Powered by a -3V~-5.5Vvolt supply, it operates as follows. It is operating at -40°C~85°C TA. The type of this D latch is JK Type. This type of FPGA is a part of the 10EP series. There should be no greater frequency than 3GHzon its output. A total of 8 terminations have been made. The object belongs to the 10EP35 family. It is powered by a voltage of 3.3V . An electronic device belonging to the family 10Ecan be found here. Surface Mount mounts this electronic component. This board has 8 pins. There is a clock edge trigger type of Positive Edgeon this device. This device is part of the FF/Latchesbase part number family. An electronic part with 2bits has been designed. As soon as 5.5Vis reached, Vsup reaches its maximum value. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 3V. On the basis of its reliable performance, this D flip flop is well suited for use with TAPE AND REEL. A total of -5.2V power supplies are needed to run it. There are 1 output lines on it. Additionally, you may refer to the D latch's additional NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V. There is -50mA output current at the high level. It is set to 50mAfor low level output current.
MC10EP35DTR2 Features
Tape & Reel (TR) package
10EP series
8 pins
2 Bits
-5.2V power supplies
MC10EP35DTR2 Applications
There are a lot of ON Semiconductor MC10EP35DTR2 Flip Flops applications.
- Frequency Divider circuits
- Single Up Count-Control Line
- Single Down Count-Control Line
- Buffer registers
- High Performance Logic for test systems
- Pattern generators
- Computers
- Shift Registers
- Convert a momentary switch to a toggle switch
- Power down protection
