MC68060RC60
| Parameters | |
|---|---|
| Package / Case | 206-BPGA |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Published | 1995 |
| Series | M680x0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Base Part Number | MC68060 |
| Speed | 50MHz |
| Core Processor | 68060 |
| Voltage - I/O | 5.0V |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| Additional Interfaces | SCI, SPI |
| RoHS Status | ROHS3 Compliant |
MC68060RC60 Description
The MC68060RC60 microprocessor offers superscalar integer performance of over 100 MIPS at 66 MHz. The MC68060RC60 comes fully equipped with both a floating-point unit (FPU) and a memory management unit (MMU) for high-performance embedded control and desktop applications. For cost-sensitive embedded control and desktop applications where an MMU is required, but the additional cost of an FPU is not justified, the MC68060RC60 offers high performance at a low cost.
MC68060RC60 Features
Four-Stage Instruction Fetch Unit (IFU)
-64-Entry Instruction Address Translation Cache (ATC)
- 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Instruction Cache
-256-Entry, 4-Way Set-Associative, Virtually-Mapped Branch Cache
-96-Byte FIFO Instruction Buffer to Allow Decoupling of the IFP and OEPs
1.6–1.7 Times the MC68040 Performance at the Same Clock Rate with Existing Compliers. 3.2–3.4 Times the Performance of a 25 MHZ MC68040.
Harvard Architecture with Independent, Decoupled Fetch, and Execution Pipelines.
Branch Prediction Logic with a 256-Entry, 4-Way Set-Associative, Virtual-Mapped
Branch Cache for Improved Branch Instruction Performance.
MC68060RC60 Applications
Communications equipment
Datacom module
Industrial
Grid infrastructure
Personal electronics
PC & notebooks
