MC68EN360AI33L
| Parameters | |
|---|---|
| Number of Terminations | 240 |
| ECCN Code | 3A991.A.2 |
| Terminal Finish | Matte Tin (Sn) |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | MC68EN360 |
| JESD-30 Code | S-PQFP-G240 |
| Supply Voltage-Max (Vsup) | 5.25V |
| Supply Voltage-Min (Vsup) | 4.75V |
| Number of I/O | 46 |
| Speed | 33MHz |
| uPs/uCs/Peripheral ICs Type | MICROCONTROLLER, RISC |
| Core Processor | CPU32+ |
| Clock Frequency | 6MHz |
| Bit Size | 32 |
| Has ADC | NO |
| DMA Channels | YES |
| PWM Channels | NO |
| Address Bus Width | 32 |
| External Data Bus Width | 32 |
| Voltage - I/O | 5.0V |
| Ethernet | 10Mbps (1) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DRAM |
| Additional Interfaces | SCC, SMC, SPI |
| Co-Processors/DSP | Communications; CPM |
| Height Seated (Max) | 4.15mm |
| Length | 31.305mm |
| RoHS Status | ROHS3 Compliant |
| Package / Case | 240-BFQFP |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Published | 1995 |
| Series | M683xx |
| JESD-609 Code | e3 |
| Part Status | Not For New Designs |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
MC68EN360AI33L Description
The MC68EN360AI33L Quad Integrated Communication Controller (QUICC?) is a versatile one-chip integrated microprocessor and peripheral combination family used in various controller applications.
The MC68EN360AI33L particularly excels in communications activities. The QUICC can be described as a next-generation MC68302, with higher performance in all areas of device operation, increased flexibility, and higher integration. The term "quad" comes from the fact that there are four serial communications controllers (SCCs) on the device. However, there are seven serial channels, including four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).
MC68EN360AI33L Features
32-bit version of the CPU32 core (fully compatible with CPU32)
Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address Lines
Complete static design (0-33 MHz Operation)
Follower mode to disable CPU32+ (allows use with external processors)
A memory controller (eight banks)
Four general-purpose timers
MC68EN360AI33L Applications
Automotive
Infotainment & cluster
Industrial
Building automation
Personal electronics
Gaming
