Parameters | |
---|---|
Factory Lead Time | 1 Week |
Package / Case | 357-BBGA |
Surface Mount | YES |
Operating Temperature | 0°C~70°C TA |
Packaging | Tray |
Published | 1995 |
Series | M683xx |
JESD-609 Code | e1 |
Part Status | Last Time Buy |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
Number of Terminations | 357 |
ECCN Code | 3A991.A.2 |
Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
HTS Code | 8542.31.00.01 |
Technology | HCMOS |
Terminal Position | BOTTOM |
Terminal Form | BALL |
Peak Reflow Temperature (Cel) | 260 |
Supply Voltage | 5V |
Terminal Pitch | 1.27mm |
Time@Peak Reflow Temperature-Max (s) | 40 |
Base Part Number | MC68EN360 |
JESD-30 Code | S-PBGA-B357 |
Supply Voltage-Max (Vsup) | 5.25V |
Supply Voltage-Min (Vsup) | 4.75V |
Speed | 25MHz |
uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
Core Processor | CPU32+ |
Clock Frequency | 33.34MHz |
Bit Size | 32 |
Address Bus Width | 32 |
Boundary Scan | YES |
Low Power Mode | YES |
External Data Bus Width | 32 |
Format | FLOATING POINT |
Integrated Cache | YES |
Voltage - I/O | 3.3V |
Ethernet | 10Mbps (1) |
Number of Cores/Bus Width | 1 Core 32-Bit |
Graphics Acceleration | No |
RAM Controllers | DRAM |
Additional Interfaces | SCC, SMC, SPI |
Co-Processors/DSP | Communications; CPM |
Height Seated (Max) | 1.86mm |
Length | 25mm |
RoHS Status | ROHS3 Compliant |
The MC68EN360VR25VL Quad Integrated Communication Controller (QUICC?) is a versatile one-chip integrated microprocessor and peripheral combination family that can be used in a variety of controller applications. The MC68EN360VR25VL particularly excels in communications activities. The QUICC can be described as a next-generation MC68302, with higher performance in all areas of device operation, increased flexibility, and higher integration. The term "quad" comes from the fact that there are four serial communications controllers (SCCs) on the device. However, there are actually seven serial channels which include four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).
32-bit version of the CPU32 core (fully compatible with CPU32)
Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-Bits) + 32 Address Lines
Complete static design (0-33 MHz Operation)
Two Independent DMAs (IDMAs)
Four general-purpose timers -Four 16-bit timers or two 32-bit timers
RISC Communications Processor Module (CPM)
Automotive
Infotainment & cluster
Communications equipment
Broadband fixed line access
Personal electronics
Connected peripherals & printers