MC68LC060RC50
| Parameters | |
|---|---|
| Package / Case | 206-BPGA |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Published | 1995 |
| Series | M680x0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Base Part Number | MC68LC060 |
| Speed | 50MHz |
| Core Processor | 68060 |
| Voltage - I/O | 5.0V |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| Additional Interfaces | SCI, SPI |
| RoHS Status | ROHS3 Compliant |
MC68LC060RC50 Description
The MC68LC060RC50 offers superscalar integer performance of over 110 MIPS at 75 MHz. The MC68LC060RC50 is fully equipped with a floating-point unit (FPU) and a memory management unit (MMU) for high-performance embedded control applications. For cost-sensitive embedded control and desktop applications where an MMU is required, but the additional cost of an FPU is not justified, the MC68LC060RC50 offers high performance at a low cost.
MC68LC060RC50 Features
1.6–1.7 Times the MC68040 Performance at the Same Clock Rate with Existing Compliers. 3.2–3.4 Times the Performance of a 25 MHZ MC68040.
Harvard Architecture with Independent, Decoupled Fetch, and Execution Pipelines.
Branch Prediction Logic with a 256-Entry, 4-Way Set-Associative, Virtual-Mapped Branch Cache for Improved Branch Instruction Performance.
A Superscalar Pipeline and Dual Integer Execution Units Achieving Simultaneous, but not Out-of-Order Instruction Execution.
An IEEE Standard, MC68040- and MC68881-/MC68882-Compatible FPU.
An MC68040-Compatible Paged Memory Management Unit with Dual 64-Entry Address Translation Caches
Dual 8-Kbyte Caches (Instruction Cache and Data Cache)
A Flexible, High-Bandwidth Synchronous Bus Interface
User Object-Code Compatible with All Earlier M68000 Microprocessors
MC68LC060RC50 Applications
Communications equipment
Datacom module
Industrial
Lighting
Personal electronics
PC & notebooks
