Parameters |
Mount |
Through Hole |
Mounting Type |
Through Hole |
Package / Case |
20-DIP (0.300, 7.62mm) |
Number of Pins |
20 |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tube |
Published |
2009 |
Series |
74ACT |
JESD-609 Code |
e0 |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
20 |
Type |
D-Type |
Terminal Finish |
Tin/Lead (Sn/Pb) |
Subcategory |
FF/Latches |
Technology |
CMOS |
Voltage - Supply |
4.5V~5.5V |
Terminal Position |
DUAL |
Peak Reflow Temperature (Cel) |
NOT SPECIFIED |
Supply Voltage |
5V |
Terminal Pitch |
2.54mm |
Reach Compliance Code |
not_compliant |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Base Part Number |
74ACT377 |
Function |
Standard |
Qualification Status |
Not Qualified |
Output Type |
Non-Inverted |
Number of Elements |
1 |
Polarity |
Non-Inverting |
Supply Voltage-Max (Vsup) |
5.5V |
Power Supplies |
5V |
Supply Voltage-Min (Vsup) |
4.5V |
Number of Circuits |
8 |
Load Capacitance |
50pF |
Number of Bits |
8 |
Clock Frequency |
140MHz |
Propagation Delay |
10 ns |
Turn On Delay Time |
3 ns |
Family |
ACT |
Logic Function |
D-Type, Flip-Flop |
Current - Quiescent (Iq) |
8μA |
Current - Output High, Low |
24mA 24mA |
Max I(ol) |
0.024 A |
Max Propagation Delay @ V, Max CL |
10ns @ 5V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
4.5pF |
Clock Edge Trigger Type |
Positive Edge |
Height Seated (Max) |
4.57mm |
Width |
7.62mm |
RoHS Status |
Non-RoHS Compliant |
Lead Free |
Contains Lead |
MC74ACT377N Overview
As a result, it is packaged as 20-DIP (0.300, 7.62mm). The Tubepackage contains it. In the configuration, Non-Invertedis used as the output. Positive Edgeis the trigger it is configured with. Through Holemounts this electrical part. A voltage of 4.5V~5.5Vis used as the supply voltage. A temperature of -40°C~85°C TAis used in the operation. D-Typeis the type of this D latch. FPGAs belonging to the 74ACTseries contain this type of chip. This D flip flop should not have a frequency greater than 140MHz. A total of 1elements are present in it. There is 8μA quiescent consumption. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. JK flip flop belongs to 74ACT377 family. An input voltage of 5Vpowers the D latch. This T flip flop has a capacitance of 4.5pF farads at the input. Devices in the ACTfamily are electronic devices. The electronic part is mounted in the way of Through Hole. Basically, it is designed with a set of 20 pins. This device exhibits a clock edge trigger type of Positive Edge. The part you are looking for is included in FF/Latches. It is designed with 8bits. Vsup reaches its maximum value at 5.5V. Keeping the supply voltage (Vsup) above 4.5V is necessary for normal operation. Its superior flexibility is attributed to its use of 8 circuits. The D latch operates on 5V volts.
MC74ACT377N Features
Tube package
74ACT series
20 pins
8 Bits
5V power supplies
MC74ACT377N Applications
There are a lot of ON Semiconductor MC74ACT377N Flip Flops applications.
- ESCC
- Bounce elimination switch
- Matched Rise and Fall
- Memory
- 2 – Bit synchronous counter
- Shift Registers
- Asynchronous counter
- Shift registers
- Counters
- Balanced 24 mA output drivers