MC74ACT564NG
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACT |
| JESD-609 Code | e3 |
| Pbfree Code | no |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Additional Feature | BROADSIDE VERSION OF 534 |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| JESD-30 Code | R-PDIP-T20 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 85MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 8μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 10.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Height Seated (Max) | 4.57mm |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
MC74ACT564NG Overview
In the form of 20-DIP (0.300, 7.62mm), it has been packaged. A package named Tubeincludes it. There is a Tri-State, Invertedoutput configured with it. It is configured with a trigger that uses a value of Positive Edge. This electronic part is mounted in the way of Through Hole. A voltage of 4.5V~5.5Vis used as the supply voltage. -40°C~85°C TAis the operating temperature. This logic flip flop is classified as type D-Type. FPGAs belonging to the 74ACTseries contain this type of chip. In order for it to function properly, its output frequency should not exceed 85MHz. There are 1 elements in it. As a result, it consumes 8μA quiescent current and is not affected by external forces. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. An input voltage of 5Vpowers the D latch. This JK flip flop has a 4.5pFfarad input capacitance. Electronic devices of this type belong to the ACTfamily. The maximal supply voltage (Vsup) reaches 5.5V. The supply voltage (Vsup) should be maintained above 4.5V for normal operation. A D flip flop with 2embedded ports is available. Additionally, it is characterized by BROADSIDE VERSION OF 534.
MC74ACT564NG Features
Tube package
74ACT series
MC74ACT564NG Applications
There are a lot of Rochester Electronics, LLC MC74ACT564NG Flip Flops applications.
- Buffered Clock
- Synchronous counter
- Shift registers
- Frequency division
- ESD performance
- Data transfer
- Supports Live Insertion
- Safety Clamp
- Single Down Count-Control Line
- Power down protection
