MC74HC112ADTG
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 1 week ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 16 |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Published | 2006 |
| Series | 74HC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Base Part Number | 74HC112 |
| Function | Set(Preset) and Reset |
| Number of Outputs | 4 |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Channels | 2 |
| Load Capacitance | 50pF |
| Clock Frequency | 35MHz |
| Propagation Delay | 235 ns |
| Turn On Delay Time | 26 ns |
| Family | HC/UH |
| Logic Function | AND, JK-Type |
| Current - Quiescent (Iq) | 4μA |
| Halogen Free | Halogen Free |
| Current - Output High, Low | 5.2mA 5.2mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 21ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| Clock Edge Trigger Type | Negative Edge |
| Length | 5mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
MC74HC112ADTG Overview
The package is in the form of 16-TSSOP (0.173, 4.40mm Width). You can find it in the Tubepackage. The output it is configured with uses Differential. It is configured with a trigger that uses a value of Negative Edge. Surface Mountmounts this electrical part. The JK flip flop operates at a voltage of 2V~6V. It is operating at a temperature of -55°C~125°C TA. It belongs to the type JK Typeof flip flops. JK flip flop is a part of the 74HCseries of FPGAs. Its output frequency should not exceed 35MHz. Despite external influences, it consumes 4μAof quiescent current. In 16terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. It is a member of the 74HC112 family. A voltage of 5V provides power to the D latch. Its input capacitance is 10pFfarads. It is a member of the HC/UHfamily of D flip flop. A part of the electronic system is mounted in the way of Surface Mount. A total of 16pins are provided on this board. Its clock edge trigger type is Negative Edge. It is part of the FF/Latchesbase part number family. It reaches 6Vwhen the supply voltage is maximal (Vsup). It is imperative that the supply voltage (Vsup) is maintained above 2Vin order to ensure normal operation. Currently, there are 2 channels available.
MC74HC112ADTG Features
Tube package
74HC series
16 pins
MC74HC112ADTG Applications
There are a lot of ON Semiconductor MC74HC112ADTG Flip Flops applications.
- Dynamic threshold performance
- Parallel data storage
- Latch
- Memory
- Frequency division
- Consumer
- High Performance Logic for test systems
- ESCC
- Communications
- Computing
