Parameters | |
---|---|
Factory Lead Time | 1 Week |
Mounting Type | Surface Mount |
Package / Case | 144-LQFP |
Surface Mount | YES |
Operating Temperature | -40°C~85°C TA |
Packaging | Tray |
Published | 2004 |
Series | MCF5225x |
JESD-609 Code | e3 |
Part Status | Active |
Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
Number of Terminations | 144 |
ECCN Code | 5A992 |
Terminal Finish | Matte Tin (Sn) |
HTS Code | 8542.31.00.01 |
Subcategory | Microcontrollers |
Technology | CMOS |
Terminal Position | QUAD |
Terminal Form | GULL WING |
Peak Reflow Temperature (Cel) | 260 |
Supply Voltage | 3.3V |
Terminal Pitch | 0.5mm |
Time@Peak Reflow Temperature-Max (s) | 40 |
Base Part Number | MCF52258 |
JESD-30 Code | S-PQFP-G144 |
Qualification Status | Not Qualified |
Supply Voltage-Max (Vsup) | 3.6V |
Power Supplies | 3.3V |
Supply Voltage-Min (Vsup) | 3V |
Oscillator Type | Internal |
Number of I/O | 96 |
Speed | 66MHz |
RAM Size | 64K x 8 |
Voltage - Supply (Vcc/Vdd) | 3V~3.6V |
uPs/uCs/Peripheral ICs Type | MICROCONTROLLER, RISC |
Core Processor | Coldfire V2 |
Peripherals | DMA, LVD, POR, PWM, WDT |
Clock Frequency | 66MHz |
Program Memory Type | FLASH |
Core Size | 32-Bit |
Program Memory Size | 512KB 512K x 8 |
Connectivity | CANbus, EBI/EMI, Ethernet, I2C, QSPI, UART/USART, USB OTG |
Bit Size | 32 |
Data Converter | A/D 8x12b |
Has ADC | YES |
DMA Channels | YES |
PWM Channels | YES |
DAC Channels | NO |
ROM (words) | 524288 |
Length | 20mm |
Width | 20mm |
RoHS Status | ROHS3 Compliant |
The MCF52258CAG66 is a ColdFire Microcontroller, CAN Controller, Coldfire V2 Family MCF5225x Series Microcontrollers. The MCF52259 microcontroller family (MCF52252, MCF52254, MCF52255, MCF52256, MCF52258, and MCF52259 devices) is a member of the ColdFire family of reduced instruction set computing (RISC) microprocessors.
This document provides an overview of the 32-bit MCF52259 microcontroller, focusing on its highly integrated and diverse feature set.
This 32-bit device is based on the Version 2 ColdFire core operating at a frequency up to 80 MHz, offering high performance and low power consumption. On-chip memories connected tightly to the processor core include up to 512 KB of flash memory and 64 KB of static random access memory (SRAM).
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used (except backup watchdog timer)
— Software controlled disable of external clock output for low-power consumption
FlexCAN 2.0B module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard data and remote frames (up to 109 bits long)
– Extended data and remote frames (up to 127 bits long)
– Zero to eight bytes data length
– Programmable bit rate up to 1 Mbit/s
— Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages
— Unused MB space can be used as general purpose RAM space
— Listen-only mode capability
— Content-related addressing
— No read/write semaphores
— Three programmable mask registers: global for MBs 0–13, special for MB14, and special for MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— Time stamp based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or 2-level trigger
On-chip memories
— Up to 64 KB dual-ported SRAM on CPU internal bus, supporting core, DMA, and USB access with standby power supply support for the first 16 KB
— Up to 512 KB of interleaved flash memory supporting 2-1-1-1 accesses
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— 40 MHz or 33 MHz peripheral bus frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+)
— Enhanced Multiply-Accumulate (EMAC) unit with four 32-bit accumulators to support 16×16 → 32 or 32×32 → 48 operations
— Cryptographic Acceleration Unit (CAU)
– Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions
– Support for DES, 3DES, AES, MD5, and SHA-1 algorithms
Industrial
Electricity Generation
Heat Metering
Office machines
Appliances
Power tools