MCIMX6G2DVM05AA
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Package / Case | 289-LFBGA |
| Surface Mount | YES |
| Operating Temperature | 0°C~95°C TJ |
| Packaging | Tray |
| Published | 2014 |
| Series | i.MX6UL |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 289 |
| ECCN Code | 5A992 |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Terminal Pitch | 0.8mm |
| JESD-30 Code | S-PBGA-B289 |
| Supply Voltage-Max (Vsup) | 1.5V |
| Supply Voltage-Min (Vsup) | 1.275V |
| Speed | 528MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR |
| Core Processor | ARM® Cortex®-A7 |
| Address Bus Width | 16 |
| Boundary Scan | YES |
| Low Power Mode | YES |
| External Data Bus Width | 16 |
| Format | FIXED POINT |
| Integrated Cache | YES |
| Voltage - I/O | 1.2V 1.35V 1.5V 1.8V 2.5V 2.8V 3.3V |
| Ethernet | 10/100Mbps (2) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | LPDDR2, DDR3, DDR3L |
| USB | USB 2.0 + PHY (2) |
| Additional Interfaces | CAN, EBI/EMI, I2C, I2S, MMC/SD/SDIO, QSPI, SAI, SPI, SSI, S/PDIF, UART |
| Co-Processors/DSP | Multimedia; NEON™ SIMD |
| Security Features | ARM TZ, A-HAB, CAAM, CSU, SJC, SNVS |
| Display & Interface Controllers | LCD, LVDS |
| Height Seated (Max) | 1.32mm |
| Length | 14mm |
| RoHS Status | ROHS3 Compliant |
MCIMX6G2DVM05AA Description
The MPC862/857T/857DSL is a derivative of Freescale’s MPC860 PowerQUICC? family of devices. It is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC862/857T/857DSL provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family.
MCIMX6G2DVM05AA Features
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
– 16-Kbyte instruction cache (MPC862P) is a four-way, set-associative with 256 sets; 4-Kbyte
instruction cache (MPC862T, MPC857T, and MPC857DSL) is a two-way, set-associative
with 128 sets.
– 8-Kbyte data cache (MPC862P) is a two-way, set-associative with 256 sets; 4-Kbyte data
cache (MPC862T, MPC857T, and MPC857DSL) is a two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
MCIMX6G2DVM05AA Applications
Electronics Point-of-Sale device
Telematics
IoT Gateway
Access control panels
Human Machine Interfaces (HMI)
Smart appliances
