MCIMX7D3EVK10SC
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Package / Case | 488-TFBGA |
| Surface Mount | YES |
| Operating Temperature | -20°C~105°C TJ |
| Packaging | Tray |
| Published | 2012 |
| Series | i.MX7D |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 488 |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.4mm |
| JESD-30 Code | S-PBGA-B488 |
| Supply Voltage-Max (Vsup) | 1.25V |
| Supply Voltage-Min (Vsup) | 1.045V |
| Speed | 1.0GHz |
| uPs/uCs/Peripheral ICs Type | MULTIFUNCTION PERIPHERAL |
| Core Processor | ARM® Cortex®-A7, ARM® Cortex®-M4 |
| Address Bus Width | 16 |
| Boundary Scan | YES |
| External Data Bus Width | 32 |
| Voltage - I/O | 1.8V 3.3V |
| Ethernet | 10/100/1000Mbps (2) |
| Number of Cores/Bus Width | 2 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | LPDDR2, LPDDR3, DDR3, DDR3L |
| USB | USB 2.0 + PHY (1), USB 2.0 OTG + PHY (2) |
| Additional Interfaces | AC'97, CAN, eCSPI, I2C, I2S, MMC/SD/SDIO, PCIe, QSPI, SAI, UART |
| Co-Processors/DSP | Multimedia; NEON™ MPE |
| Security Features | A-HAB, ARM TZ, CAAM, CSU, SJC, SNVS |
| Display & Interface Controllers | Keypad, LCD, MIPI |
| Height Seated (Max) | 1.1mm |
| Length | 12mm |
| RoHS Status | ROHS3 Compliant |
MCIMX7D3EVK10SC Description
The i.MX 7Dual family of processors represents NXP’s latest achievement in high-performance processing for low-power requirements with a high degree of functional integration. These processors are targeted toward the growing market of connected and portable devices.
MCIMX7D3EVK10SC Features
ARM Cortex-A7 plus ARM Cortex-M4—Heterogeneous Multicore Processing architecture enables the device to run an open operating system like Linux/Android on the Cortex-A7 core and an RTOS like FreeRTOS? on the Cortex-M4 core.
Two ARM Cortex-A7 cores—The processor enhances the capabilities of portable, connected applications by fulfilling the ever-increasing MIPS needs of operating systems and applications at the lowest power consumption levels per MHz.
Multilevel memory system—The multilevel Cortex-A7 memory system is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The processor supports many types of external memory devices, including DDR3, DDR3L, LPDDR2 and LPDDR3, NOR Flash, NAND Flash (MLC and SLC), QSPI Flash, and managed NAND, including eMMC rev.
Power efficiency—Power management implemented throughout the IC enables features and peripherals to consume minimum power in both active and various low-power modes.
Multimedia—The multimedia performance is enhanced by a multilevel cache system, NEON? MPE (Media Processor Engine) coprocessor, a programmable smart DMA (SDMA) controller.
Up to two Gigabit Ethernet with AVB—10/100/1000 Mbps Ethernet controllers supporting IEEE Std 1588 time synchronization.
Electronic Paper Display Controller (EPDC)—The processor integrates an EPD controller that supports E Ink color and monochrome panels with up to 2048 x 1536 resolution at 106 Hz refresh, 4096 x 4096 resolution at 20 Hz refresh, and 5-bit grayscale (32-levels per color channel)
MCIMX7D3EVK10SC Applications
Audio
Connected devices
Access control panels
Human-machine interfaces (HMI)
Portable medical and health care
IP phones
Smart appliances
Point of Sale
eReaders
Wearables
Home energy management systems
