MM74HCT273N
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74HCT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Matte Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | NOT APPLICABLE |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | NOT APPLICABLE |
| JESD-30 Code | R-PDIP-T20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 68MHz |
| Family | HCT |
| Current - Quiescent (Iq) | 8μA |
| Current - Output High, Low | 4.8mA 4.8mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 37ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 6pF |
| Propagation Delay (tpd) | 46 ns |
| Length | 26.075mm |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
MM74HCT273N Overview
As a result, it is packaged as 20-DIP (0.300, 7.62mm). A package named Tubeincludes it. T flip flop is configured with an output of Non-Inverted. In the configuration of the trigger, Positive Edgeis used. There is an electronic component mounted in the way of Through Hole. The JK flip flop operates at a voltage of 4.5V~5.5V. Temperature is set to -40°C~85°C TA. D-Typeis the type of this D latch. In terms of FPGAs, it belongs to the 74HCT series. Its output frequency should not exceed 68MHz. D latch consists of 1 elements. As a result, it consumes 8μA quiescent current. The number of terminations is 20. Power is supplied from a voltage of 5V volts. The input capacitance of this T flip flop is 6pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. In this case, the D flip flop belongs to the HCTfamily. As soon as 5.5Vis reached, Vsup reaches its maximum value. Normally, the supply voltage (Vsup) should be above 4.5V.
MM74HCT273N Features
Tube package
74HCT series
MM74HCT273N Applications
There are a lot of Rochester Electronics, LLC MM74HCT273N Flip Flops applications.
- Instrumentation
- Buffer registers
- Load Control
- Divide a clock signal by 2 or 4
- Circuit Design
- CMOS Process
- Frequency Divider circuits
- Matched Rise and Fall
- EMI reduction circuitry
- Data storage
