MPC755CVT400LE
| Parameters | |
|---|---|
| Package / Case | 360-BBGA, FCBGA |
| Surface Mount | YES |
| Operating Temperature | 0°C~105°C TA |
| Packaging | Tray |
| Published | 2001 |
| Series | MPC7xx |
| JESD-609 Code | e2 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 360 |
| ECCN Code | 3A991 |
| Terminal Finish | TIN COPPER/TIN SILVER |
| Additional Feature | ALSO REQUIRES 2.5V OR 3.3V SUPPLY |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | MPC755 |
| JESD-30 Code | S-PBGA-B360 |
| Supply Voltage-Max (Vsup) | 2.1V |
| Supply Voltage-Min (Vsup) | 1.9V |
| Speed | 400MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Core Processor | PowerPC |
| Clock Frequency | 100MHz |
| Bit Size | 32 |
| Address Bus Width | 32 |
| Boundary Scan | YES |
| Low Power Mode | YES |
| External Data Bus Width | 64 |
| Format | FLOATING POINT |
| Integrated Cache | YES |
| Voltage - I/O | 2.5V 3.3V |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| Height Seated (Max) | 2.77mm |
| Length | 25mm |
| RoHS Status | ROHS3 Compliant |
MPC755CVT400LE Description
The MPC755 is targeted for low-cost, low-power systems and supports the following power management features—doze, nap, sleep, and dynamic power management. The MPC755 consists of a processor core and an internal L2 tag combined with a dedicated L2 cache interface and a 60x bus. The MPC745 is identical to the MPC755 except it does not support the L2 cache interface.
MPC755CVT400LE Features
Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving two speculations)
— Up to one speculative stream in execution, one additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating
branch delay slots
Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to six independent units (system, branch, load/store, fixed-point
unit 1, fixed-point unit 2, floating-point)
— Serialization control (predispatch, postdispatch, execution serialization)
Decode
— Register file access
— Forwarding control
— Partial instruction decode
Completion
— Six-entry completion buffer
— Instruction tracking and peak completion of two instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization, and all instruction flow changes
Fixed point units (FXUs) that share 32 GPRs for integer operands
— Fixed Point Unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed Point Unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
